JPS616938A - Error preventing circuit of digital data - Google Patents

Abstract

PURPOSE:To prevent a range error of a reproduced digital data signal by adopting the constitution that the circuit consists of a holding means, a counter means, a comparison means and a gate processing means in obtaining the reproduced digital data signal from an input digital data signal. CONSTITUTION:MSB, LSB of the input digital data signal are inputted to an input terminal 1. The MSB of the input digital data signal is stored in a flip-flop 6 and a comparison discriminating signal is outputted to an AND gate 12 from a comparator 9 when the bit less then the maximum bit of the designated absolute value by the input range bit data signal is inputted, and an output is switched to the comparison discriminating signal, and since the MSB signal is an ineffective bit signal not displaying the level, the level of the reproduced ditital data signal does not exceed the range designated by the input range bit data signal and the range error of the reproduced digital data signal is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error prevention circuit for a digital digital signal that is applied to the reproduction or reception of a digital digital signal formed by sampling an analog audio signal or the like.

[Prior art]

Conventionally, when performing I'CM modulation on an analog audio signal, for example, the solid line analog audio signal is sampled at a constant sampling interval Ts, as shown in FIG. The analog audio signal is input to the converter, and the number of quantized bits N (N
bit) binary code digital data signal, i.e. P
Modulate to CM signal. Note that MSB and LSB in the figure indicate the most significant bit and the least significant bit, respectively, and in FIG. 2, MSB, 2.8.4. ..., N-2
°N-], aligned on the LSB.

By the way, when recording digital tape signals that have been sequentially formed as described above on a magnetic tape or a recording dinuque, or when transmitting them via a medium such as radio waves, for example, when an analog audio signal is a stereo signal, continuous transmission of the same channel is required. Each digital data signal of the same channel is grouped into one group with a predetermined number of samples of digital data signals, and for each group, the absolute value of the group is determined based on the digital data signal with the largest absolute value within the group. It is conceivable to form a range bit data signal for displaying the maximum level of , that is, for displaying the maximum absolute value, and to record or transmit an information signal consisting of the digital data signal and the range bit data signal.

For example, in the case of audio transmission for satellite television broadcasting, a stereo analog audio signal is quantized with a quantization bit count of 16.
Each of the 48 consecutive digital data signals of the right and left channels is modulated into a digital data signal that has the maximum absolute value among the 48 digital data signals. A range bit data signal is originally formed and an information signal comprising the formed digital data signal and the range bit data signal is transmitted. Note that each digital data signal becomes a 2'' complement U binary code signal, that is, a code signal expressed in two's complement.

By the way, the most significant bit in one digital data signal formed by one sampling, that is, MSB, is used to indicate the positive or negative of the digital data signal, so the remaining 15 bits are the absolute value of the digital signal. It represents the level value of.

And in the case of audio transmission of satellite television broadcasting, the third
As shown in the figure, the absolute value level is set to 215〉～≧214
, 214 >~≧213 , 218 >~≧212
, 212 >~≧211 , 211 >~, and range numbers 0, 1 .
2-. 3.4 and "000'' for each range number.

Ilo 01", "010", "011", "1
A range bit data signal of 00'' is assigned to each.

Therefore, 1 consisting of 48 digital tape signals as described in
As shown in Fig. 4(a), if the digital tape signal with the largest absolute value in a group has an MSB of 1° and a second bit of O, the digital take signal will be at a negative level based on the MSB of 1. Since it is a signal of The bit data signal becomes "ooo"2 based on FIG.

In addition, the digital data signal with the maximum absolute value is shown in Figure 4 (b
), the MSB, 2nd to 6th bits are O1.
If the 7th bit is 1, the digital data signal is a positive level signal based on the MSB 0, so the 7th bit is 1.
Bit 1 becomes the most significant bit of the valid bits representing the level/V value, and the absolute value level is located in the range of 2'1〉~.At this time, the range bit data signal of the group is shown in Figure 3. Originally it became “JOO”.

Furthermore, the digital data signal with the maximum absolute value is shown in Figure 4 (
As shown in C), the MSB, second and third bits are 0.
．． If the fourth bit is 1, the digital data signal becomes a positive level signal, and the 4th bit, 1, becomes the most significant bit of the valid bits representing the level/l/value. The level is located in the range of 213> to 212, and at this time, the range bit data signal of the group becomes "O] 0" based on FIG.

First, when receiving satellite television broadcasting, errors in the range of the reproduced digital data signal when obtaining the reproduced digital data signal having the level value of each received digital data signal, for example, From the company in Showa 5
As disclosed in Broadcasting Technology's "Audio Signal System for Satellite Television Broadcasting" published in April 2010, errors in the range of the reproduced digital data signal are corrected based on the error correction code of the immediately preceding frame. is prevented.

However, in order to perform the correction based on the error correction code of li''lJiho, it is necessary to provide a very complicated arithmetic circuit, which complicates the configuration of the receiver and leads to high curvature.

Note that the range bit data signal is used only to control the expansion of the received digital data signal, and is not used to prevent errors in the range of the reproduced digital data signal.

[Purpose of the invention]

This invention does not take into account the points in I'iJ, I-1,
It is an object of the present invention to prevent errors in the range of a reproduced digital data signal when obtaining a student digital data signal from a reproduced or received digital data signal at low cost with a simple 1 m structure.

[Structure of the invention]

The present invention provides a range for maximum display of absolute values in digital data signals sequentially formed by sampling analog signals and the predetermined number of digital data signals formed for every predetermined number of consecutive digital data signals. When reproducing or receiving an information signal having a bit data signal,
holding means for holding invalid bits that do not represent a level value consisting of the most significant bit or an inverted bit of the most significant bit of the input digital data signal that is input sequentially from the most significant bit by reproduction or reception; Based on a counter means for counting clock signals synchronized with each bit of an input digital data signal, and a comparison between a count signal of the counter means and an input range bit data signal input by reproduction or reception.

Comparing means for outputting a comparison discrimination signal after the input of the maximum bit of the absolute value set by the input current bit signal of the input digital data signal, and a period until the comparison discrimination signal is input. The output of the invalid bit of the holding means is held, and after the comparison and discrimination signal is input, the pressure is switched to the input digital data of rrlJ, and each bit until the comparison and discrimination signal is input is the invalid bit. , and each bit after the input of the comparison and discrimination signal is formed by each pin 1- of the input digital data signal after the input of the comparison and discrimination signal '2! f
1. and gate processing means for outputting a reproduced digital data signal.

〔Effect of the invention〕

Therefore, according to the circuit for preventing errors in digital data of the present invention, bits inputted by reproduction or reception can be obtained by using a simple and inexpensive configuration consisting of a holding means, a counter means, a comparison means, and a gate processing means. Displays the level jv value of each pip of the reproduced digital data from to the maximum bit of the absolute value set based on the input range bit data signal input by reproduction or reception, regardless of the input digital data signal. This makes it possible to prevent invalid bits from occurring and errors in the range of reproduced digital data signals.

〔Example〕

Next, this invention will be explained in detail with reference to the drawings from FIG. 5 showing one embodiment thereof.

In other words, as in the case of audio transmission for satellite television broadcasting, the number of quantized bits 1 is sequentially formed for each channel by sampling a stereo analog audio signal.
The predetermined number formed for each group consists of a digital take signal consisting of a binary code signal of 6-2←-embryment and a predetermined number of consecutive digital data words of the same channel, for example, 48 sampling numbers. A case will be described in which an information signal consisting of a range pitch 1-tater signal for displaying the maximum absolute value in a digital data signal, that is, a 3-bit range bit data signal shown in FIG. 3 is received.

First, the received information signal is separated by channel,
The technical data signal and range bit data signal for each channel are taken out, and the taken out digital data signal of the left or right channel, that is, the input digital data signal is input to the terminal input terminal (1) in Fig. 5. is input.

By the way, the input signal data input to the input terminal (1) has the most significant bit, MSB, the second . Third. ..., 15th. It is formed by the 16 least significant bits, ie, J and SB, and is input to the input terminal (12) in order from tdM8B.

In addition, as shown in FIG. 6(b), the clock input terminal (2) receives a clock signal synchronized with the input digital data signal shown in FIG. A clock signal that rises at the trailing edge is input. Note that the clock signal is internally generated based on the received information signal.

Furthermore, as shown in FIG. 6 ((d)), the first gate signal that rises at the leading edge of the MSB of the input signal output signal and falls at the trailing edge of fiLsB is input to the gate input terminal (3). , the first gate signal is also internally generated based on the received information signal.

The clock signal at the input terminal (2) is input to the clock terminal (C1O) of the first flip-flop (4) of D5, and the first gate signal at the input terminal (3) is input to the data terminal (d ), the flip-flop (4) latches the first gate signal at the rising edge of the clock signal, and the flip-flop (4) latches the first gate signal at the rising edge of the clock signal.
) from the Q output terminal (q) of
A second gate signal is output which falls at the rising edge of the clock signal following the trailing edge of the clock signal.

Further, the second gate signal is a data terminal (d) of a second flip-flop (5) of D type, a clock terminal (ck) of a third flip-flop (6) of D5 forming a holding means, and a counter forming a counter means. It is input to the clear terminal (C4) of (7).

The input digital data signal of the input terminal (1) is input to the data terminal (d) of the flip-flop (6), and the input category take signal is latched at the timing of the rise of the second gate signal.

Therefore, the flip-flop (6) latches M, SB of the input digital data signal, and the Q output terminal ((1) of the flip-flop (6) latches the latched MSB
The signal 7, that is, the MSB signal is ignored, and the Q output terminal (
9) is an inverted signal of the latched MSB signal.

That is, the counter-axis Δ4SB signal is output.

In addition, the clock signal of the input terminal (2) is connected to the inverter (8
The inverted clock signal is input to the clock terminal (ck) of the flip-flop (5), and the flip-flop (5) latches the second gate signal at the rising edge of the inverted clock signal υ, that is, at the falling edge of the clock signal.

Therefore, the Q output terminal (q) of the Noritsubu flop (5) is connected to the U, 6th gate signal. A third gate signal, that is, a third gate signal that rises at the trailing edge of MSB of the input digital data signal and falls at the fall of the clock signal after the second gate I1 falls is output.

Further, the counter (7) is cleared and reset at the moment when the input digital signal is latched, and the counter (7) is cleared and reset in order from the lower digit.
Qa, Qb, Qc, Qd output terminal (CI) 11
), (Qb), (qC), and (Qd) are all held at low level, that is, 0, and when the second gate signal rises, the input digital data signals M and S B are input to the flip-flop (6). When latched, the clear reset of the counter (7) is released.

Then, the inverted clock signal of the first inverter (8) is input to the clock terminal (ck) of the counter (7). 1 is counted up for each trailing edge of the input digital data signal.
01", 2nd pin 1- for input digital data
At the trailing edge of , the count value signal becomes '0010'.

Furthermore, each output terminal (qa) to (qd) of the counter (7)
) is the output of the digital comparator ``a(9
) A, o, AI, A2.13 Input terminals (ao), (a+) in order from the lower digit.

It is input to (a2) and (a3).

On the other hand, range bit data input terminal (]
Oa), (+01)), (IOC) have input category /'
The range bit data signal received with the /l/l/meter, that is, each bit in order from the LSB of the input range bit data signal of the group to which the input data signal belongs is input, and the input terminals (10a) to (
The bit signals of 10G) are input to the comparator (9) in order from the lower digit until the input of all input digital data signals of the group is completed.
), (1]1), and (b2), respectively. Note that the B3 input terminal ( ) 8) of the lower digit of the 82 input terminal (+12) of the ratio M device (9) is grounded.

Then, the comparator (9) compares the content of the count value signal of the counter (7) with the content of the manual range bit data signal of the input terminals (LOA) to (10G), and the content of the count value signal of the counter (7) is compared. When the content of the count value signal becomes larger than the content of the input range bit data signal, the output of the Q output terminal (q) of the comparator (9) changes from high level to low level.

That is, while the content of the count value signal is greater than the content of the input range bit data signal, the comparator (9
) A comparison determination signal of 0 is output from the output terminal (q).

By the way, the count value signal of the counter (7) changes the count value every time one bit of the input digital data signal is input.
The input range bit data signal is counted up one by one from "'ooo"', and the input range bit data signal is counted up by one from the maximum range, with the maximum range being "'ooo", as is clear from Figure 3.
Each time the range goes down, the contents count up from "o o o".

Therefore, input terminals (IOa) to (10b) are supplied with, for example, a range bit data signal of range number 0, that is, 'ooo
” input range bit data signal is input, and if the maximum absolute value of the group to which the input digital data signal belongs is specified as smaller than 215, input of the MSB of the input ticle data signal is completed. counter(
7) When the content of the count value signal reaches a value "0001" which is larger than the content of the manual range bit data signal, that is, when the second bit, which is the 214th bit of the input digital data signal, is input, the 61st As shown in Figure (f), a comparison discrimination signal is output from the comparator (9).

Similarly, the input range bit data signals of range numbers 1 to 4 are input to the input terminals (IOa) to (100), and the maximum absolute value of the group to which the input digital take signal belongs is 214, 213, 212. , 2I
+ each, the third . 4th. Fifth. 6th bit [・
As shown in FIG. 6(g), a comparison discrimination signal is outputted from the ratio 1 articulator (9) each time the signal is input.

In other words, the comparator (9) starts outputting the comparison discrimination signal at the bit of the input digital data signal corresponding to the input range P1- which is one level lower than the most significant bit of the range specified by the theta signal. is input.

And input terminal (LOA) ~ (IOC) with range number 2.
If the input range bit data signal is input, a comparison determination signal is output from the comparator (9) when the input range bit data signal starts to be input.

Furthermore, the third gate signal of the Q output terminal (q) of the flip-flop (5) and the output signal of the Q output terminal (q) of the comparator (9) form a logic gate section C forming gate processing means.
11) from the input of the second pin 1- of the input digital data signal to the input of the comparison discrimination signal, that is, the second pin 104 of the input digital data signal. While the third bit is input, the AND gate (1
The output signal of the AND gate Q4 is held at 1, and the output signal of the AND gate Q4 becomes 0 from the input of the comparison discrimination signal until the end of input of the LSB of the input digital data signal.

Note that when the comparison discrimination signal based on the input range bit data signal of range number 0 is input to the ant game 104, the comparison discrimination signal is output at the same time as the third gate signal rises. As shown in , the output of AND gate 4 is held at 0, and each input range bit data signal of range numbers 1 to 4 is output to AND gate
When the input digital signal ! is input to the input digital signal, the output of the AND gate α is input as shown in FIG. 6 (1). When the second to fifth bits of the signal are input, they change from 1 to O, respectively.

That is, the output signal of the AND gate 0 is held at 1 from the start of input of the second bit of the input digital data signal into which the third gate signal is input until the comparison discrimination signal is input, and the output signal of the comparison discrimination signal is It is held at 0 from the time of input until the end of input of the LSB of the input digital data signal.

The output signal of the AND gate 04 is inputted to one input terminal of the second AND gate Q3 and the second inverter (14), and at this time, the output signal of the flip-flop (6) is inputted to the other input terminal of the AND gate Q3. Since the output terminal (q) is connected, the AND gate (1 → outputs the MSB signal of the Q output terminal (q) of the flip-flop (6) until the comparison judgment signal is input, and the range number is When the comparison discrimination signal is input based on the input range bit data signal of 2, the flip-flop (6) The MSB signal of the Q output terminal (q) is output.

By the way, since the input digital data signal is a binary data signal with 2-to-2 combination, if the MSB of the input digital data signal is O, it indicates that the input digital data signal is positive, and in this case, The level value of the input technical data signal is indicated by 1.0 of each bit below the second bit, and conversely, the level value of the input digital data signal is
If SB is 1, it indicates that the input digital data signal is negative, and in this case, the level value of the input digital data signal is indicated by the inverted value of 1.0 of each bit from the second bit onward.

It has the same value as the 1 bit when it is 0 or negative, and when the comparison discrimination signal is input, the AND gate 04 outputs l.
The validity of the invalid bit described in \iJ will be output.

If a comparison discrimination signal is input at the time of inputting the 4th bit of the input digital data signal based on the input range data signal of range number 2, M'SB of the input digital data signal of input terminal (1) is 0. During the input of the second and third bits of the input digital data signal, the output signal of the AND gate (1) is input to O.

On the other hand, since the output signal of the AND gate θ4 is inverted by the inverter (14), an inverted signal that becomes +VC after inputting the ratio 1 bite discrimination signal from the inverter (04) to one input terminal A of the third AND gate (15) is output.

Since the input digital data signal of input terminal (1) is input to the other input terminal of Antogame-1-051,
Based on the above-mentioned inverted signal, the AND gate (151) outputs each bit signal of the input digital data signal after the input of the comparison discrimination signal, and the comparison discrimination signal is input when the fourth bit of the input digital data signal is input. In this case, Antogame 1.01 outputs each bit signal of the 4th bit to LSH of the human-powered digital data signal.

Furthermore, the AND gate (13, Q output signals) are outputted to the data output terminal 07 via the OR gate αQ.

Therefore, the reproduced digital data signal obtained at the output terminal θ is determined by the difference between the input period of the second bit to T and SH, which indicates the level value of the input digital data signal, at the input of the comparison discrimination signal. Each bit is formed by an invalid bit based on the MSB signal of the AND gate 0■, and each bit after the input of the comparison discrimination signal is formed by each bit of the input digital data signal after the input of the comparison discrimination signal. .

Therefore, M S H of the input digital data signal is O
In this case, if the comparison discrimination signal is no longer output at the 4th pin 1- of the relevant digital data signal and the maximum absolute value of the cruise to which the relevant input digital data signal belongs is specified as 213 or less, the input digital data signal is 2. The first bit of the reproduced digital data signal corresponding to the third bit. The second bit is formed by 0, which is an invalid bit, based on the input digital data signals M and B, respectively, and
The third bit to LSB of the reproduced digital data signal is formed by the fourth bit to LSB of the input digital data signal, and the second bit of the input digital data signal is 1 due to a transmission error, for example. In this case, the first bit of the reproduced digital data signal is held at 0, and the range of the level value of the reproduced technical data signal does not exceed the range specified by the input range bit data signal, so that an error in the range of the reproduced digital data signal is prevented.

As explained above, according to the embodiment, when a reproduced digital data signal is formed from an input digital data signal of 2゛→combination, the MSB of the input digital data signal is held in the flip-flop (6), and
Input range bit 1 of input digital data signal - AND gate Q is output from comparator (9) when bits less than the maximum bit of the absolute value specified by the take signal start to be input.
By effectively outputting the comparison and discrimination signal, the gate section qυ is held at the output of the M8B signal of the flip-flop (6) until the comparison and discrimination signal is input, and the gate section 01 is maintained at the output of the M8B signal of the flip-flop (6) until the comparison and discrimination signal is input. ) is switched to the output of the input digital data signal, and at this time, since the MSB signal is an invalid bit signal that does not display a level value, the reproduced digital data signal can be output even if there is a range error in the input digital data signal. , each upper bit up to the bit specified by the input range bit data signal is held as an invalid bit, and the level value of the reproduced digital data signal does not exceed the range specified by the input range bit data signal, and the reproduction is continued. Range errors in digital data signals are prevented.

Although the range of the reproduced digital data signal is incorrect, the flip-flops (4) to (6), counter (7), comparator (9), 77 gate 0a, Q3. This can be prevented with a simple and inexpensive configuration consisting of Q5+, Okay-hQQy, etc.

In the case of the above embodiment, input digital data signal number 2
“Formed by the binary code signal of each conbriment,
Since MSJ3 of the input digital data signal becomes an invalid bit, the input digital data signal was held in the flip-flop (6), but the input digital data signal was not formed by the offset binary binary code signal, and the input If the inversion of 84SB of the digital data signal becomes an invalid bit, the Q output terminal of the flip-flop (6) (
q) in the AND gate 03, and by holding the inverted bit of ΔISB in the flip-flop (6),
It is possible to obtain the same effects as in the above embodiment.

Further, in the embodiment described in mJ, only the input digital data signal of the left or right channel A channel is inputted to the input terminal (1) to form the reproduced digital data signal of the left or right channel, but for example, the input digital data signal of both channels is It is also possible to input take signals alternately for each group to form reproduced digital data signals for both channels.

Furthermore, it is of course applicable to cases where the number of bits of the input digital data signal is other than 16 bits, and when reproducing information signals recorded on recording media such as magnetic tapes and recording disks. Of course, the signal may be a technical data signal that is an analog signal other than an audio signal.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of sampling of an analog audio signal, Fig. 2 is an explanatory diagram of a digital data signal formed by sampling in Fig. 1, Fig. 3 is an explanatory diagram of a range bit data signal, and Fig. 4 (a ) to (C) are explanatory diagrams of digital data signals, respectively. Figure 5 and the following drawings show an embodiment of the digital data error prevention circuit of the present invention. Figure 5 is a block diagram, and Figure 6 (a). -(1) are timing charts for explaining the operation of FIG. (6)...Flip-flop, (7)...Counter, (9)...Comparator, (1υ...Logic gate section.

Claims (1)

[Claims] (1) A range bit for displaying the maximum absolute value in digital data signals sequentially formed by sampling analog signals and the predetermined number of digital data signals formed for each consecutive predetermined number of digital data signals. When reproducing or receiving an information signal having a data signal, invalid bits that do not represent a level value consisting of the most significant bit or an inverted bit of the input digital data signal that is input sequentially from the most significant bit by reproduction or reception. a holding means for holding, a counter means for counting clock signals synchronized with each bit of the input digital data signal, and a comparison between the counted value signal of the counter means and the input range bit data signal input by reproduction or reception; Based on the above, the comparison means outputs a comparison discrimination signal after the input of the maximum bit of the absolute value set by the input range bit data signal of the input digital data signal, and the holding means until the comparison discrimination signal is inputted. The input digital data signal is held at the output of the invalid bit of the means and is switched to the output of the input digital data signal after the comparison discrimination signal is input, and each bit until the comparison discrimination signal is input is set to the invalid bit. and gate processing means for outputting a reproduced digital data signal in which each bit of the input digital data signal after the input of the comparison/discrimination signal is formed by each bit of the input digital data signal after the input of the comparison/discrimination signal. Digital data error prevention circuit.