JPS6174877U

JPS6174877U -

Info

Publication number: JPS6174877U
Application number: JP15981884U
Authority: JP
Priority date: 1984-10-24
Filing date: 1984-10-24
Publication date: 1986-05-20

Description

[Brief explanation of the drawing]

第１図は本考案の実施例のブロツク図、第２図
はアナログ入力信号における各部の波形説明図で
ある。１：アナログ入力信号、２：入力段増幅回路、
３：ＡＤ変換器、４〜６：メモリ、７：メモリア
ドレス信号、８：メモリ書き込み信号、９〜１１
：メモリ制御回路、１２〜１４：プリトリガ設定
回路、１５：プリトリガ設定信号、１６：トリガ
信号、１７：トリガ回路、１８〜２０：書き込み
クロツク、２１：トリガレベル、２２：トリガポ
イント、２３〜２５：プリトリガ点、２７：第１
のメモリ期間、２８：第２のメモリ期間、２９：
第３のメモリ期間。 FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of waveforms of various parts in an analog input signal. 1: Analog input signal, 2: Input stage amplifier circuit,
3: AD converter, 4-6: memory, 7: memory address signal, 8: memory write signal, 9-11
: Memory control circuit, 12-14: Pre-trigger setting circuit, 15: Pre-trigger setting signal, 16: Trigger signal, 17: Trigger circuit, 18-20: Write clock, 21: Trigger level, 22: Trigger point, 23-25: Pre-trigger point, 27: 1st
memory period, 28: second memory period, 29:
Third memory period.

Claims

[Scope of utility model registration request]

In a waveform storage device that performs AD conversion on an analog signal and stores the converted digital value, there are a plurality of storage elements for each amount of information of the aforementioned analog input signal, and a plurality of storage elements corresponding to the analog input signal. A trigger circuit controls the trigger point at which writing starts, and multiple pre-trigger points are set to store the waveform before this trigger point in proportion to the amount of information, and the writing to the aforementioned storage element is controlled. 1. A waveform storage device comprising: a pre-trigger setting circuit for controlling a memory element; and means for controlling a storage element in response to write control from the trigger circuit and the pre-trigger circuit.