JPS61765A - Wire harness tester - Google Patents

Abstract

PURPOSE:To enable the checking of a plurality of wire harnesses with one continuity tester, by arranging memory circuits for normal connection in the number as obtained by dividing the number of connection lines, a memory selection key and one memory circuit for controlling operation to be connected to a setting keyboard. CONSTITUTION:Based on a program stored in an ROM 12, a microcomputer 7 sends an instruction signal P1 to a distribution circuit 18 to distribute the number of circuits na-nn of test relay lines 6a-6n to normal connection mode setting RAMs 11a-11n through checking circuits 151-15n. When a start key on an addressing keyboard 8 is pressed, address contents set on the RAMs 11a-11n are read out sequentially to be collated with the output of the corresponding switching circuit 15 and when there is no abnormality, the program is advanced by one step to collate. The results are shown on a display circuit 16. When another wire harness is connected during the checking, it is checked together with the earier one.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a continuity testing device for wire harnesses used, for example, in automobiles and electrical equipment.

(Prior Art) Connection line circuits that connect various devices, for example, connections between devices such as headlights, tail lights, and other electronic devices installed in automobiles and power supplies, or connections between devices. As shown in Figure 1, a so-called wire harness (1) wired according to the installation position of various devices is made, and this is fixed in a predetermined position on the vehicle body (2) that is sent in the assembly line. , their input and output ends are connected using a connector (6) or the like. By the way, in order to ensure reliability of operation in the wiring harness, each connection wire (4)
It is important that the connector is correctly connected to the connector used for connection to equipment, etc., without errors. But the connecting line (4)
There is a tendency for the number of vehicles to increase as the performance of automobiles and the like increases. For this reason, for example, as shown in Fig. 2 (α), the connector contacts ■1 to e1 and ■6 to e3...
... is connected as a single line by the connection line (4, As shown in b) ■
Even if it is rare, it is unavoidable that an erroneous connection such as a blank line occurs between 3 and e6.

Therefore, in order to automatically, quickly, and reliably discover connection errors and make repairs, a continuity testing device, so-called wire harness checker, as shown in FIG. 3 is generally used. This device consists of a connector group (5), that is, a wire harness (the input end of which is placed on the test stand (6) and connected to the connector (5) provided on the test stand (6))
The contact, the output end is the e-contact, and the test relay wire (6
) for the number of test connection circuits to be connected (5
Connector group (5) consisting of 1X52)...(5n) ■ Processing circuit (7) For example, microcomputer (7)
(hereinafter referred to as microcontroller) For example, by pressing [1] on the address designation keyboard (8) corresponding to the contact number of the connector, and then pressing the single wire connection key (9), you can designate the address and check the connection status. l 11+.

For example, after pressing [2] on the keyboard (8), specify the address by pressing the blank line key (1), and then press the second
The memory circuit for writing/reading (11XRAM) in which the normal connection state shown in FIG.
A read-only memory in which an operation management program for performing program stellar up is set by the address designation keyboard (8) for checking the setting contents and the output of the checking switching circuit group (15). circuit(
12). Then, the microcomputer (7) starts the operation by pressing the start key (15), temporarily stops the operation when an error occurs due to verification, and starts the operation again from the beginning when the return key (14) is pressed. ■ Check For example, as shown in FIG.
and the e-side contact is connected to the switching transistor Tr2.
At the same time, connect the potential appearing at the e side contact to the positive polarity side of the power supply E via ++ 11t ++ 01+
Check switching circuits (15,) (152) each consisting of a level detector that detects the signal as a signal.
・Equipped with (15n). And the switching transistor Tr1. Tr2 is sequentially turned on in the order of ■1 to e11 and ■2 to e2 contacts by the switching signal from the microcomputer (7), allowing current to flow through each connection wire, thereby establishing the normal connection shown in Figure 2 (cL). Figure 2 (
When the contact ■1 to e1 is connected by a single wire as shown in b), the level detector 11+, ■2 to e2. ■6~
A check switching circuit group (15) that sends out a signal of "0" when the line is empty like e3.

■ The display circuit (16) advances in synchronization with the switching of the check switching circuit group (15) according to a command from, for example, the microcomputer (7), and sequentially displays ■ and the e-contact number, for example, as shown in Figure 2. Although the single wire connection between ■5 and e5 as shown in (cL) is a normal connection state, it is a blank wire as shown in Figure 2 (b) and the check switching circuit (is ,) when the emission 1 is ``0'', the microcomputer (7) stops due to the verification operation, stops the forwarding by stopping the sending of commands from the microcomputer (7), displays the contact number where the abnormality has occurred, and at the same time generates an abnormal sound. The circuit (16) is formed from the following, and in short, performs a series of determination operations as shown in the flowchart shown in FIG. 5 to check the continuity of the wire harness.

Note that there are also cases in which the settings of the memory circuit for setting the normal connection mode are compared with the output of the check switching circuit, and the control of each circuit is performed not by the program (software) K described above, but by a hardware circuit. be.

(Problems to be Solved) By the way, the number of connection wires in a wire harness usually differs depending on the type of car used. Therefore, in general, as a continuity test device, we select the memory capacity of the memory circuit for setting the normal connection mode, the number of switching circuits for checking, etc., targeting the wire harness with the maximum number of connected wires.
This is installed exclusively on each test stand to check continuity. However, in this case, when the number of connected wires of the wire harness is less than the maximum number of test connected wires of the continuity test device, the usage efficiency decreases.

In the case where a wire harness with a number of connection wires smaller than the maximum number of test connection wires of the continuity test device is continuously tested, within the range of the maximum number of test connection wires of the continuity test device, the present invention
This makes it possible to check multiple tubes of wire harnesses with one continuity testing device, thereby making effective use of the continuity testing device.

[Structure of the invention]

(Structure and operation for solving the problems) FIG. 6 is a diagram showing an example of an apparatus for implementing the present invention, and the features of the present invention are as follows. The item (■) relates to the configuration of the microcomputer (7). That is, when the maximum number of connection line circuits that can be checked is N, the memory circuits for normal connection mode setting (11s (11b), (11c),・・・・・・(
11n) and one operation management program setting memory circuit (12). In addition, n memory selection keys (17) of the same number as the number of memory circuits for setting the normal connection mode are provided, and by switching the selection, each of the memory circuits (11 (iib)... (11n)) for setting the normal connection mode is provided. Then, use the setting keyboard (8), single wire key (9), empty wire key (10), etc. to select the wires and harnesses (1) to be tested.
The main point is that the normal connection mode of αX1b) (1n) can be set independently.

■ is a distribution circuit (18), that is, when the maximum number of testable connection line circuits is N, it is formed by N gate circuits,
By the command signal P sent out based on the program to be described later set in the operation management program setting memory circuit (12), the normal connection mode setting memory circuit (11α) (11b)...-(1in. ), the number of test connection line circuits nα of the off diagram (α) is set to nα.

nb, ...... nn address, check switching circuit (15
) has N check switching circuits (is, ) (is,
, )...(1'5n) is connected to the normal connection mode setting memory circuit (11 (ZXl 1b
)...Distribute to (11c). Then, the output of each check switching circuit is connected to each normal connection mode setting memory circuit (1
A distributing circuit (18) is provided, which constitutes a circuit that compares the setting contents of 1st (11b)...(11n) every time the program is stepped up by the memory circuit for setting the operation management program (12). At the point. That is, the memory circuit for setting the operation management program (12), as shown in the flow chart shown in FIG.
Read the set number nα of connection line circuits, and compare it with the maximum number N of connection line circuits. When the result is 11LL<N, send a distribution command signal to the distribution circuit (18). And when this is finished, Φ memory circuit for normal connection mode setting (iib)
Read the setting connection line circuit number nb of ■111Z+11b
≦N, the result is +1cL+11b+11c
When ≦N, [F] sends a distribution command signal to the distribution circuit (18). The following comparison operations are performed in the same manner in order, and the distribution is made.
In addition, when the number of distributed circuits up to that point exceeds the maximum number of testable connection line circuits N during the verification process, a program is set to send an error signal indicating that the check is impossible, and the distribution as described above is performed. is what causes the action to take place.

■ is in the memory circuit (12) for setting the operation management program.
Memory circuit for setting each regular connection mode ('lHz) (11
b)...(11n) and the following program for comparing the outputs of the respective assigned checking switching circuit groups (15).

That is, as shown in the flowchart shown in Figure 9, 1. Read the contents of the first address set in the normal connection mode setting memory circuit (11α), and 2. Compare this with the output of the corresponding check switching circuit. do. Next, read out the contents of the first address set in @regular connection mode setting memory (11'b), and compare it with the output of the corresponding check switching circuit. Continuing with the memory circuit for setting the normal connection mode. If there is no abnormality, the program is stepped up by one step [F] and the normal connection mode setting memory circuit (IIQ (
The present invention is provided with a program that sequentially reads out the contents of the 2nd address of each of iib) (11n) and sequentially compares the contents with the output of the corresponding check switching circuit.

(2) is that a display circuit (16) having the following configuration is provided. That is, each test stand (6
α) A memory circuit for normal connection mode setting, connected to the microcomputer (7) by a cable (19) with a length reaching (6b)...(6n), and using a memory circuit (12) for setting an operation management program. (11α)(t i b)・
Each time the (tin) program steps up, each step is performed by a signal sent, and the contact and e-contact numbers are sequentially displayed. At the same time, the start of the step is the memory for setting each regular connection mode. circuit(
Display circuit (16α) for displaying the number of memory circuits for normal connection mode setting, which is performed by a signal sent when reading the first address contents of (ntL) (ub) (11n).
(16b)...(16n) are provided.

■Display circuit (16cL) (16b)... (1
6n) is provided with a start key and a return key, and the start key starts the microcomputer (7) and displays the display circuit (1).
Step 6) is started, and the display circuit (1) is started by pressing the return key.
6) The continuity test device is operated remotely by updating the display and interrupting the stepping circuit.

In this way, for example, when a wire harness is connected to one of all the test stands and a start key belonging to that one is pressed, only the display circuit belonging to that one is operated and checked. Also, if another wire harness is connected and the start key is pressed during this check, the first connected wire harness will be checked at the same time, and the first connected wire harness will be checked. When the return key is pressed, the check of the next connected wire harness is continued, and the check of the wire harnesses connected one after another is performed.

(Effect of the invention) In this way, one continuity testing device can check multiple wire harnesses within the maximum number of testable connection circuits, so the checking ability of the continuity testing device can reduce waste and improve usage efficiency. Furthermore, according to the present invention, not only can a plurality of wires/. Therefore, since each tester is not influenced by other checks, the checking work can be streamlined.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the wire harness, Figure 2 + eL) (b
) is an explanatory diagram of the normal and abnormal states of the connection line circuit, Fig. 5 is an explanatory diagram of the conventional device, Fig. 4 is a switching circuit diagram for checking, and Fig. 5 is an operation flow diagram of the memory circuit for setting the operation management program. , FIG. 6 is an example of an embodiment of the present invention, and an off view (α)
(b) is an explanatory diagram of the relationship between the settings of the memory circuit for setting the normal connection mode and the distribution of the check switching circuit by the distribution circuit;
8 and 9 are operation flow diagrams of the memory circuit for setting the operation management program. (1)...Wire harness (2)...Vehicle body, (
6)...Connector, (4)...Connection line, (5)...
... Connector group, (6) ... Test stand, (6) ...
Test relay line, (7)...Microcomputer, (8)...
・Address specification keyboard, (9)...Single line connection key, (10) --- Blank line key, (11) (11
(11b)-(11n)--Memory circuit for setting normal connection mode, (12)...Memory circuit for setting operation management program, (13)...Start key, (
14)... Return key, (15)... Check switching circuit group, (16)... Display circuit group, (17)
...Memory selection key, (18)...Distribution circuit,
(19)...Cable. Patent applicant: 1 person other than Shindengen Kogyo Co., Ltd.

Claims (1)

[Claims] A processing circuit including a memory circuit for setting an operation management program and a memory circuit for setting a normal connection mode of the connection line circuit under test, and a processing circuit that is sequentially switched by an output signal from the memory circuit to sequentially cause current to flow through the connection line circuit under test. The checking switching circuit sends out a signal indicating the connection status, and the processing circuit compares the output of the checking switching circuit with the written content of the normal connection mode setting memory circuit, and detects the abnormality under test. In a continuity testing device equipped with a display circuit that displays the position of a connection line circuit, the memory circuit for setting the normal connection mode is formed by any plurality of memory circuits for setting the normal connection mode, and the number of memory circuits for setting the normal connection mode is the same as that number. It is formed so that the normal connection mode can be set independently using an address setting keyboard, single line keys, blank line keys, etc. that can be switched by keys, and also includes the above checking switching circuit by the above memory circuit for setting the operation management program. The wire harness circuit is distributed to the plurality of memory circuits for setting the normal connection mode, and the output of each switching circuit for checking the distribution by the processing circuit is compared with the setting contents of each memory circuit for setting the normal connection mode. A distribution circuit is provided,
In addition, a plurality of display circuits each having a start and return key connected via a cable are provided corresponding to the plurality of memory circuits for setting the normal connection mode, and
Switching of the check switching circuits distributed by the above distribution circuit and checking the output of the check switching circuit with the settings of the memory circuit for setting the normal connection mode are performed for each address of the memory circuit for setting the normal connection mode. A wire harness testing device characterized in that the testing is performed using a memory circuit for setting an operation management program in which a program to be performed in series is set.