JPS6177191A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory, and particularly to a write circuit suitable for reducing the amplitude of a word line drive circuit.

[Background of the invention]

As a background art of the present invention, for example, υBO in rJ, NO
.

T, TAMUR^, M, NAKAMAE, H,5II
IRAKI, T., IKUSHIMA.

T,AKASHI,)1. MAYUMI, T, UB
OTA, T, NAKAMURA, “A4.5ns
Access Time IK X 4 Bit
ECL ) IAM” IEEHVOL 5c-18,N
There is a technique described in a50CT 1983 p515-p519J.

In general, in integrated circuits, reducing the amplitude of a signal is effective in increasing the speed of the circuit. Especially in bipolar memory,
The delay time in the word line drive circuit accounts for a large portion of the access time, and reducing the amplitude of the word line drive circuit can greatly contribute to speeding up. However, in conventional write circuits, the amplitude of the word line drive circuit is limited to a fairly large value, and it is difficult to reduce the amplitude below this value.

This relationship will be explained below. An outline of a conventional memory cell array and peripheral circuit is shown in FIG. 1, and the operation of this circuit will be briefly explained below. First, one of the word line drive circuits XD, for example, XDl, is selected and the word line or □ becomes a high level Vllll. All other word lines, such as x2, are unselected and go to a low level vIL. In this state, one of the digit line drive circuits YD, for example, YD
l is selected and the digit line is set according to the cell information,
D.

A read current flows from the cell to either of the cells. In this way, cell MC1□ is selected. The explanation will now be made assuming that in this cell, the transistor Q□ is on and the transistor Q1□ is off. Transistor Qt at this time
The base potential of □ is V, □-1. The base potential of transistor Qi2 is V. Let it be o-a. It is also connected to the same digit line as cell MC, □.

Even in unselected cells, for example cell MC21, transistor Q2□ is off, transistor Qz
Assume that z is on. Transistor Q at this time
The base potential of 2□ is vo. , □, and the base potential of the transistor Q□ are set to VaX-□. Also, in this figure, IaT□,
■、? □ is the holding current, 1.1. I□ is a read current. When reading in this circuit, the write command signal (W
E) read/write circuit RWI71 output line R
W1. Both RW2 (7) potentials are V Q 1- a and V
, , is set to the intermediate potential Vrefc.

At this time, the read current Ill flowing through the digit line D1
flows from the transistor with the highest base potential among the transistors connected to digit line D1. This relationship will be explained with reference to FIG.

In this figure, (a) shows the potential relationship of the transistor connected to the digit line D1 during reading, and (b) shows the potential relationship of the transistor D2. Furthermore, (c) and (d) show the potential relationship during writing. In other words, as can be seen from Fig. 2, the read current 11
□ flows from transistor Q1□. Similarly, the readout current flowing to digit line D2 from FIG. flows from the cell potential reference transistor QIIz. Therefore, cell potential reference transistor Q is used. , Qo, the sense circuit S detects in which direction the read current flows, information stored in the cell can be read out as data output.

During writing, the output of the read/write circuit RW is triggered by the write command signal (WE)! R.W. Eng.

One side is set to V,l, depending on the information to write RW,. −
, the lower potential ■w, and the other one to the potential V refc. Hereinafter, a case will be considered in which the potential of the output line RW of the read/write circuit RW is set to Vrefc, and the potential of RW is set to vwL. The read current ll11 flowing through the digit line D1 is caused by the transistor Q as in the case of reading.
□6 that flows from 1 is the readout current that flows to digit line D2. As can be seen from FIG. 2, the base potential of the cell potential reference transistor Q0 is . . Since vWL is lower than -6, it flows from transistor Q, □.

At this time, the base potential of the transistor Q□□ decreases due to the voltage drop of the load connected to the collector of the transistor c12.

From the point when the voltage drops below V refc, the transistor Q
tt is turned off, the read current □ begins to flow from the cell potential reference transistor Qvx, and the information in the cell is reversed. In this way, arbitrary information can be written into the cell.

Now, in the case of conventional writing methods like this, there is no read current during writing. v0□1. is not shunted by transistor Q□2゜Q2z. is V. Must be lower than o-a.

Normally, vol-□ is V because a potential difference of 100 to 200 mV is required to prevent the transistors that make up the current switch from causing shunt. . -6 Yosu 100-200m
V must be low.

If vcl-1 and ll do not satisfy the above conditions, the read current □ that should originally flow from the transistor Q1□.

Transistor Q of the unselected cell. Also diverted from.

This is because writing to the selected cell MC1□ is not completed because the current flowing from the transistor Q12 is reduced.6 On the other hand, the word, mu active open circuit low level vxL and vc
Since x-na are approximately the same potential, due to the above restrictions, vx
, , must be lo~200 mV lower than v a o + a. This condition determines the output amplitude of the word line drive circuit.

Furthermore, it is generally known that increasing the read current can shorten the delay time in the cell.

However, in the case of the cell shown in Figure 1, when the current flowing through the cell is increased, the Schottky barrier diode (hereinafter abbreviated as SBD) S
Both BDl and 5BD2 are turned on, and the transistor Q*
In order to clamp the base potentials of both Qix to a potential lower than VXll by the voltage drop of SBD, transistors Q□1. The potential difference between the bases of Q1□ disappears, making it impossible to hold information. (See FIG. 3) Therefore, a cell as shown in FIG. 4 has been devised. In the case of this cell, even if the current is increased, the base-to-base potential difference is maintained at an appropriate value because of the resistor connected in series with the SBD (see FIG. 4). If you use a cell that can set the read current to a large value like this,
Since the potential at 0°8 is lower than that of the cell shown in Figure 3, due to the above-mentioned limitations, vl must be set lower than when using the cell shown in Figure 3, and the amplitude of the word line drive circuit increases, causing This was seen as a problem when reducing the delay time.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory having a low amplitude word line drive circuit suitable for high-speed operation.

[Summary of the invention]

In order to achieve the above object, we devised a writing method in which writing is performed without any read current flowing through the digit line depending on the information to be written.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

Conventionally, the base potential of the cell potential reference transistors QR1 and Ql12 used for both reading and writing is V.
Fixed to refc. Then, new transistors Qwt+Qwz for reading W are connected to the read current switching transistors QvttQwz so as to form current switches, respectively. The cell shown in FIG. 4 is used. The operation of this circuit will be explained below.

Assume that cell MC11 is selected, and in cell MC,□, transistor Q1□ is on, and transistor Qtt is on.
is off, and the base potential of transistor QU□ at this time is V. L-8% Base potential of transistor Q1m is V. Let it be o4. Also, an unselected cell connected to the same digit line as cell MC11, for example MC
, □, transistor Q21 is off, transistor Q
. is on, and the base potential of transistor Q21 at this time is ■. . −11, the base potential of the transistor Qzz is v a z −* a .

At the time of reading, the output line WllW2 of the write circuit W
is a potential V lower than the high level V□ of the digit line drive circuit.
□, turn off the transistor Q wit Qwz,
Reading can be performed by flowing a read current in the same manner as in the conventional case.

During writing, the output line W□ of the writing circuit W.

Depending on the information to be written to w2, one is set to a potential vw□ higher than the V resistor, turning on the writing transistor connected to it, and the other is set to vwvL, turning off the writing transistor connected there. do.

Now turn on the writing transistor Q w t, Q, □
Consider what happens when you turn off . At this time, the readout current
□ flows from the writing transistor Q, and the read current flows from the cell potential reference transistor Ql1m, so the current flowing to the selected cell MC□1 is only the holding current.

Connected to the collector of the transistor in the cell,
The voltage drop due to the load decreases until V6N
-a+V co -a transistor Q 1L
+ The base potential of Qxi is vct-x as shown in Figure 4.
, lt rises towards Vao-xa.

At this time, the read current I is kept to such an extent that it is not divided between the cell potential reference transistor QR2 and the transistor Q1m.
. . -xl is higher than V rafc, transistor Q
1□ can be turned on completely and information can be written. However, if sV66-1B does not satisfy the above conditions, transistor Q12 cannot be turned on completely, and the potential relationship between the bases of transistor Q1□eQs may be reversed, or even if it is reversed, the potential relationship between the bases is Because the potential difference between is small, information is easily destroyed.For example,
In the case of the cell shown in FIG. 3, vo. -X, is V refc
However, the present invention cannot be applied if:
In the case of the cell shown in FIG. 4, v0°-X is sufficiently higher than V refc and the present invention is applicable.

Next, the output amplitude of the word line drive circuit in the present invention will be described.

In the conventional write method, vK& is limited by writing, whereas in the present invention, it is limited by reading. That is, at the time of reading, V3. , from Vrefc to 100
It is only possible to raise the potential to ~200 mV lower.

By applying the present invention, conventional V. . , 8 to 100~
Vx, which could only be raised to a potential 200 mV lower, can now be raised to a potential 100 to 200 mV lower than Vrefc. This relationship will be explained with reference to FIG. FIG. 6(,) shows the output amplitude ΔV, of the conventional word line drive circuit, and FIG. 6(b) shows the output amplitude AV,' of the word line drive circuit when the present invention is applied. For example, the amplitude of the word line drive circuit can be reduced from the conventional 27
It can be reduced to about 3.

Further, in the present invention, the time required for the base potential of the transistor of the selected cell to exceed V refc accounts for a large proportion of the write period. Therefore, V r only during the writing period.
Writing time can be shortened by lowering efc than when reading.

In this case, it is not necessary to lower the base potential of both by making the bases of the cell potential reference transistors Qll□ and QOt common as in the example in FIG. 5, but by separating the bases of the cell potential reference transistors Q11 f QII2. Then, depending on the information to be written, only the base potential of the cell potential reference transistor connected to the same digit line as the transistor to be turned on in the cell needs to be lowered.

FIG. 7 shows an example in which the present invention is applied to a memory circuit to which a word line discharge circuit is added to shorten the falling time of the word line. Δ■1 is the word line discharge current. In the case of such a circuit, when the read current is not applied to the selected cell during writing, the word line discharge current flows in the cell in addition to the holding current, but V'QO-1m in Fig. 4 is equal to Vr.
The present invention can be applied to such a circuit by setting the word line discharge current to be equal to or higher than efc.

FIG. 8 shows an example of a write circuit used in the present invention. WE and C3 are a write command signal and a chip selection signal, respectively, and these are negative logic.

DI is a write information input signal, which is positive logic. O
D is an output prohibition signal, mV connected to the output circuit.
lll t Vans z Vans is a reference potential of each circuit. Further, W□ and W2 are output lines of the write circuit. DI when C5 is high level.

Regardless of WE, this circuit's output line W1. Both W and W become low level VIII, and writing is prohibited.

OD becomes high level and prohibits data output.

When 3 guns are at low level and WE is at high level, output mw□
Both t WZ become low level V Y W & and reading is performed, OD becomes low level and the read information is output as data output. 3 guns are low level W
When E is at a low level, the output line W,.

W2 becomes a high level VwYY on one side and V□ a low level due to DI, and writing is performed, and OD becomes a high level, prohibiting data output during writing.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the output amplitude of the word line drive circuit to about 273 compared to the conventional one, and the delay time in this circuit can be shortened, which has the effect of shortening the access time accordingly. Furthermore, according to the present invention, which enables a low output amplitude of the word line drive circuit, it is possible to lower the power supply voltage compared to conventional circuits, and if the power supply voltage is the same, it is possible to increase margin against transistor saturation. becomes.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a part of a conventional cell array and peripheral circuit, FIG. 2 is an explanatory diagram showing the base potential relationship of a conventional cell and a cell potential reference transistor during reading and writing, and FIG. FIG. 4 is a DC characteristic diagram of a memory cell, FIG. 5 is a circuit diagram showing an embodiment of the present invention, FIG. 6 is an explanatory diagram comparing the amplitude of a conventional word line drive circuit with that of the present invention, and FIG. The figure is a circuit diagram showing an example in which the present invention is applied to a circuit with a word line discharge circuit.
/ Country I+u IR2 Figure 2 (0-) (b) (C) (L
:L) 3rd z 4th nightmare 5th part 6th figure (α) (6)

Claims (1)

[Claims] In a memory having a current switching circuit for sharing read current between multiple pairs of digit lines, when information is written to a selected memory cell, one of the read currents flowing through the pair of digit lines is switched according to the written information. A semiconductor memory characterized by being provided with a current switching circuit that stops current flowing out from a digit line.