JPS6177367A - Gaas ic - Google Patents

Abstract

PURPOSE:To obtain the IC formed by on-chip construction of FETs almost equal to each other in characteristic and rectangular to each other in gate finger orientation, by a method wherein part of FETs orients a gate finger in parallel with the (010) plane, and the other orients a gate finger in parallel with the (001) plane. CONSTITUTION:Si ions are selectively implanted to a semi-insulation GaAs substrate 21, and an operating layer 22 is formed by activation on annealing. Next, a TiW alloy is deposited and selectively removed into a gate finger 31, and an SiO2 film 41 is adhered by CVD. si ions are implanted with he mask of the gate finger 31, and an N<+> type high impurity concentration layer 23 is formed by activation on annealing. Then, electrodes 32 made of AuGe alloy to form ohmic contact and Ni and electrodes 33 produced by laminating Ti, Pt and Au are formed, resulting in the completion of a MESFET.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a gallium arsenide integrated circuit, and particularly to a gallium arsenide integrated circuit in which a field effect transistor is integrated on a chip as an active element.

(Prior art) The development and practical application of gallium arsenide integrated circuits (GaAs ICs) has been particularly remarkable in recent years, with successive announcements of logic ICs with 1000 logic gates and static random access memories with 1000 to 4000 bits. It has reached nine times. In this way, GaAs-IC is GaA, (1
A Schottky barrier gate field effect transistor (MISFET), wiring, etc. are integrated on the 00) surface.

GaAa-ICs with large scale integration usually have a threshold voltage (
MISFETs with VT ) of less than approximately 1■ are constructed, but in most cases, in GaAs ICs with this stiffness, the gate fingers of MISFETs in the same chip are parallel to the Schete (011) plane, or all (0
11) FFIT having gate fingers oriented parallel to the (011) plane, actively oriented parallel to the (011) plane, and actively oriented parallel to the (011) plane;
FIT with gate fingers oriented parallel to the plane
were rarely mixed on the same chip. The reason is that GaAs-M E with a VT of less than approximately 1v
In 8 F E T , there is a large difference in the electrical characteristics of a FIT with a gate finger parallel to (011) (1) and an FET with a gate finger parallel to the (011) plane.Another reason is, for example, Applied, published in 1983.
Physics Letters (Applied Phys
ics Letters) Volume 42, No. 3, No. 27
As described on pages 0 to 271.

The main gate length for practical use of GaA,-IC is approximately 1
．． VT of GaAs・MES FET of 5 μm or less
As the gate length becomes shorter, the FET with gate fingers parallel to the (oii) plane and (011) ii
There is a phenomenon in which the difference increases between FETs having gate fingers parallel to i, and there is an inconvenience that the difference in VT of FETs having gate fingers perpendicular to each other varies due to variations in the key lengths that occur during the manufacturing process.

(Problems to be Solved by the Invention) For the reasons mentioned above, orienting all the gate fingers in the same chip in one direction imposes a large restriction on the pattern layout of 10, and limits the degree of freedom in design. This results in an increase in design man-hours.

In addition, an FE with 25 gate fingers orthogonal to each other
Compared to the case where the IC is mounted on a TIL, the integration density per unit area of the IC must be lower, and as a result, the operating speed of the IC is reduced due to an increase in the chip area and an accompanying increase in the wiring length. This led to a significant decline in demand due to large-scale agglomeration.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a gallium arsenide integrated circuit comprising an on-chip FIT that has the same #1 ratio and whose gate fingers are orthogonal to each other. .

(Means for Solving the Problems) The gallium arsenide integrated circuit of the present invention is made of gallium arsenide (1
00) Gallium arsenide J formed by on-chip circuit elements including a plurality of field effect transistors electrically connected on a surface [In a circuit, some of the field effect transistors are (010)
The present invention is characterized in that it is a charge effect transistor oriented parallel to the plane, and the other is a field effect transistor whose gate fingers are oriented parallel to the (001) plane.

The present invention is applicable even if the above field effect transistor is a Schottky #wall gate type field effect transistor.

(Example) Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are diagrams showing the experimental results that form the basis of the present invention. FIG. 1 shows the drain bias IV and gate bias of GaAs-ME8FFiT with gate length Q and 81J1 formed on the same wafer. Drain voltage I (Tnsx) and mutual conductance (J7
It shows the change in the gate finger orientation direction of the threshold voltage (n, ) and the threshold voltage (7 digits).

The orientation direction of the gate fingers in FIG. 1 is 0 when parallel to the (011) plane 11, as shown in FIG.
1 is parallel to the surface 12 as 90', and as shown in the same figure (
45. on the (100) plane 13 in the counterclockwise direction relative to 00.
The direction 46 times counterclockwise relative to 90 is defined as 135.

Figure 1 shows that GILAs-
II) gX t which is Sa of ME S F ET
In.

This is an experimental fact that shows that vT is facilitated, but what is noteworthy is that the gate finger orientation direction is 45° and 1
The 35° MESFETs are almost identical. Furthermore, Figure 2 shows ■ of GaAl・MBf9FB'l゛!
This is the result of an experimental study on how the dependence of the gate length on the gate length changes depending on the orientation direction of the gate fingers.
The characteristics of the GaAs-Ml 8 k″ET are almost the same as I, and the MIFET with a gate length of approximately 1.5 μm or less
It is clear that even if gate length variations occur during the manufacturing process, the VT of the 90, A, MISFET is almost the same by arranging the gate fingers in these two directions.

Next, FIGS. 4(a) to 4(d), which explain the manufacturing method of the embodiment of the present invention using drawings, are
, A, . FIG. 2 is a cross-sectional view showing the order of steps for explaining the manufacturing method of ME8FET.

First, as shown in FIG. 4(a), Si ions are selectively implanted into the semi-insulating Q2A@substrate 21 at an acceleration energy of 30 keV and a dose of 2.8 x 10" cm, and activated by annealing. A working layer 22 is formed. Next, a TiW alloy is deposited to a thickness of 0.5 μm.
Gate fingers 31 are formed by selective removal.

Next, as shown in #%4 figure (b), CV D (Ch
chemical vapor deposiliorL)
8 i 0 * Wk with thickness 2000s due to i
41 is applied.

Next, as shown in FIG. 4(C), the gate finger 3
8i ion acceleration energy 200 using 1 as a mask
KeV, implanted at a dose of 6 x 10"cm, activated by annealing, and formed into a high impurity concentration layer 23 of n[.
form.

Next, as shown in FIG. 4(d), an electrode 32 made of an AuGe alloy and Ni for forming an ohmic contact and an electrode 33 made of a laminated layer of T++Pt and Au are formed. Complete ', 7f'.

FIG. 5 is a perspective view of an embodiment of the present invention, and FIG. 6 is an equivalent circuit diagram of the embodiment shown in FIG.

In FIG. 5, 50 is a semi-insulating GaA, s substrate.

51 digits (010), 52 digits (001), 53 is (1
00) side. Gate fingers 611 and 62a of FETs 61 and 62 are parallel to the (001) plane.
63 and 64 gate fingers 631 and 64a (
010) It is oriented parallel to the plane, and the name ii'
Needless to say, when the geometric dimensions of the ETs are the same, the 49 characteristics of each FET are almost the same.

(Effect of the invention) As explained above in detail, according to the present invention.

Even if GaAs-ME8FETs with gate fingers oriented perpendicular to each other are mounted on an IC, the characteristics of these MisFETs can be made equal regardless of variations in gate length due to process. G, A - The degree of freedom in IC pattern design was improved, and the number of design steps could be reduced. Also, IC
Since more patterns can be accommodated in a chip unit area, the chip area can be reduced, the wiring length can be shortened, and the operating speed of the IC can be improved.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams showing the experimental results that are the basis of the present invention, Figure 3 is a ninth schematic diagram explaining the experimental results that are the basis of the present invention, and Figure 4 is an example of an implementation of the present invention. FIG. 5 is a cross-sectional view showing the order of steps for explaining an example manufacturing method, and FIG. 5 is a perspective view of an example of the present invention. FIG. 6 is an equivalent circuit diagram of the embodiment shown in FIG. 5. 11... (011) plane, 12... (o
xT) plane, 13... (100) plane, 21...
... Semi-insulating GaAs substrate, 22 ... Active layer, 23 ... Ion implantation layer, 3L61a, 62a
163a164a---Gate finger, 32
．． 33...Ohmic IEffl, 4t, old...
StO, film, 50...semi-insulating 1! GaA-rich substrate, 51...(010) plane, 52...(
ooi) plane, 53... (100) plane, 61,6
2,63.64・・・・・・F'BT 1st drawing grass 2nd gate, &◇&'Wn leather 3yJ 'πji run /7 smoke - ri ゞ1 - □□-V

Claims (2)

[Claims] (1) In a gallium arsenide integrated circuit in which circuit elements including a plurality of field effect transistors electrically connected on the (100) plane of gallium arsenide are integrated on a chip,
Some of the plurality of field effect transistors are field effect transistors in which gate fingers are oriented parallel to the (010) plane, and others are field effect transistors in which gate fingers are oriented parallel to the (001) plane. A gallium arsenide integrated circuit characterized by being a field effect transistor. (2) The gallium arsenide integrated circuit according to claim (1), wherein the field effect transistor is a Schottky barrier gate type field effect transistor.