JPS6178169A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, and in particular to a technology for increasing the integration of memory elements, improving electrical stability, and preventing deterioration. is one MOS
The present invention relates to a technology that is applicable and effective for EEP-ROMs consisting of FETs.

[Background technology] EEP-ROM (Electrically erasable programmable ROM)
) The 9MNOS type and floating gate type are generally known.

By the way, the conventional EEP-ROM has the following problems. That is, in the MNOS type, there is a limit to the number of times the stored contents can be read after changing. This is because the interface between the 5i02 film 6 and the Si3N4 film 7 deteriorates during repeated read operations.

Furthermore, when configured as a memory array, it is necessary to connect a switching MOS element in series with the MNOS memory element. In addition, in the floating gate type, deterioration of the film quality of the 5i02 film 16 and 5i02
A drawback is that charges trapped in the membrane 16 impair the stability of the electrical characteristics of the memory cell. Furthermore, there is a problem in the degree of integration of memory cells due to alignment margins during the formation of thin oxide film regions.

[Object of the Invention] An object of the present invention is to provide an EEP-ROM in which one memory cell is formed by one element, which improves the degree of integration.
Moreover, it provides a stable semiconductor device with no limit to the number of times of reading.

The above-mentioned and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention A brief outline of typical inventions disclosed in this application is as follows.

That is, a floating gate is formed above a semiconductor region formed on a semiconductor substrate via a first insulating film, and a MIS element is further formed on a second insulating film using SOI (silicon on insulator) technology. ing. During writing and erasing, a voltage is applied between the semiconductor region and the MIS element, and charge can be stored or extracted from the floating gate, so that an EEP-ROM can be formed with one element as a 1-bit memory cell. . Also, when reading, the semiconductor region is grounded and the MIS
Because it can be done by elements.

There is no charge loss from the floating gate and there is no deterioration of the first insulating film, so it is possible to dramatically increase the number of read operations and to achieve stability over time of the memory cell.

[Example 1] An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows an embodiment of the present invention, where E E P −r<
It shows the cross-sectional structure of one memory cell of OM. In the figure, reference numeral 20 is a semiconductor substrate.

For example, it is a P-type (first conductivity type) Si semiconductor single crystal substrate. A semiconductor region 21 of a conductivity type opposite to that of the substrate 20, that is, an N type (second conductivity type), is formed on one main surface of the substrate 20. This semiconductor region 21 contains, for example, arsenic (A
s) is formed by ion implantation.

A first insulating film 22 is formed on the upper surfaces of the P type substrate 20 and the N + type semiconductor region 21 . This first insulating film 2
2 is a 5i02 film formed, for example, by surface thermal oxidation on the surface of the substrate 20, and has a thickness of about 100 angstroms.

As will be described later, charges are tunnel-injected or discharged into the floating gate 23 through the first isolation film 22. A polysilicon floating gate 23 is formed on the first insulating film 22 . Floating gate 23 is formed by polysilicon deposition and photoetching. It is preferable that the floating gate 23 is located above the semiconductor region 21 and within the width of the semiconductor region 21.

However, this alignment margin does not have to be strict.

Furthermore, the substrate 20 and the floating gate 23
A 5i02 film, which is the second insulating film 24, is formed thereon. A MOS and II device are formed on this second insulation board 24 using SOI technology.

That is, a polysilicon layer serving as a MoS element is deposited above the floating gate 23 and etched into a predetermined shape. A channel region 26° and a drain region 27 are formed. After the polysilicon layer is deposited on the second insulator [24], it is single-crystalized by a laser beam. Further, the entire polysilicon layer is P of the same -a type as the substrate 20.
Doped with type impurities. Therefore, channel region 2
6 is a P-type silicon semiconductor. Furthermore, a third insulating film 28, 5i, is formed by thermally oxidizing the surface of this polysilicon layer.
02 film is formed. This third insulating film 28 is MO
This is the gate oxide film of the S element.

After forming the gate oxide film 28, a gate electrode (control gate) 29 of the MO5i element is formed of polysilicon. Through this control gate 29 and the third insulating film 28, impurities of the second conductivity type that form the source and drain are ion-implanted.
The type source or drain regions 25 and 27 are formed in a self-aligned manner. The code 30 is SiO□ or PSG (
Protective insulating film such as phosphosilicate glass, code 31゜3
2 are source or drain extraction electrodes, respectively.

The operation of the EEP-ROM having the above element structure will now be described.

First, in order to write, the N+ type semiconductor region 21 is set to the ground potential, and the source and drain N+ type semiconductor regions 21 are set to the ground potential.
5. Set 27 to high potential. In this case, electrons are injected from the N+ type semiconductor region 21 into the floating gate 23 by Fowler-Notheim (F-N) tunneling.

Therefore, vt and h of the MOSJt1 child become high. Next, in order to erase, the negative charges accumulated in the floating gate 23 are removed by lowering the source and train N+ type semiconductor regions 25, 27 to the ground potential and raising the N+ type semiconductor region 21 to a high potential. '' type semiconductor region 21.

In this way, writing and erasing can be performed.

For reading, the stored contents can be taken out via the control gate 29 of the MOS element depending on the level of v and h. In this case, since the N4' type semiconductor region 21 is set to the ground potential, there is no charge loss from the floating gate 23 during reading, and the number of readings can be greatly increased. Also.

Since the readout is based on the current flowing through the channel region 26 of the MO5i element, there is no deterioration of the first insulator W;422.

[Embodiment 2] FIG. 2 shows an EEP-ROM which is a second embodiment of the present invention.
This figure shows the cross-sectional structure of one memory cell. Parts that have the same or equivalent functions as those shown in Figure 1 include:
The same reference numerals are given and the explanation thereof will be omitted.

This embodiment is an example in which insulating films 22a and 22b having different thicknesses are used in place of the insulating film 22 shown in FIG. The insulating films 22a and 22b are made of 5i02 films formed by thermal oxidation of the surface of the semiconductor substrate 20.

tens of angstroms (e.g. 20 angstroms)
The thin insulating film 22a is formed approximately at the center of the semiconductor region 21 and below the channel region 26, and functions as a tunnel insulating film when charges are tunneled between the semiconductor region 21 and the floating gate 23.

The insulation film 221) has a thickness of several hundred angstroms (for example, 300 angstroms).
This is advantageous in terms of manufacturing since there is no need to provide on the semiconductor substrate an insulating film that is thicker than the insulating film 22a and has the same thickness as the tunnel insulating film.

[Effects] As explained above, since the MOS element is formed on the floating gate via the insulating film using SOI technology, it is possible to obtain a 1 MO3FET/1 bit EEP-ROM. Further, the source and drain regions of the MOS element can be formed in a self-aligned manner using the control gate as a mask. Furthermore, since readout is performed by the MoS element, the first insulating film between the floating gate and the semiconductor region in the substrate is resistant to deterioration.

Although the invention made by the present inventor has been specifically described above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Not even.

For example, it goes without saying that the conductivity types of the embodiments can all be reversed.

[Field of Application] The present invention can be widely applied to EEP-ROM, for example, EE
It can also be applied to P-ROM on-chip microcomputers, dedicated processors for TV tuners, VTR program reservations, etc.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the semiconductor device of the present invention.
Figure 2 is a cross-sectional structural diagram of a 1-bit floating gate type EEP-ROM.
FIG. 2 is a cross-sectional structural diagram of an EP/ROM.

Claims (1)

[Claims] 1. A second conductivity type opposite to the first conductivity type formed in a semiconductor substrate of the first conductivity type, and a first insulating film formed on the diffusion layer. and a MIS element formed on the semiconductor substrate and the floating gate via a second insulating film,
The S element includes a channel region of a first conductivity type formed at a position facing the floating gate, a source and a drain of a second conductivity type formed on both sides of the channel region, and a third conductivity type on the channel region. 1. A semiconductor memory device comprising a control gate formed through an insulating film. 2. The semiconductor memory device according to claim 1, wherein a part of the first insulating film is made thinner than the other part.