JPS6180346A - Input/output control device - Google Patents

Abstract

PURPOSE:To make the processing ability of a composite system efficient by selecting a start priority means and an interruption priority means with priority between plural host devices and plural I/O devices. CONSTITUTION:A start/interruption priority selection circuit 9 is formed in an I/O control device 2 connected between plural host devices 1a, 1b and plural I/O devices 3a-3n. The circuit 9 outputs an interruption priority signal output section T1 and a start priority signal output section T2 to start decision circuits 4a, 4b to circulate the ratio of the T to T2 between 1 to 1 and 1 to 10 at a fixed variation period. When an interruption signal is generated from the devices 3a-3n to the device 2, the control part 6 decides the sections T1, T2 of the circuit 9 and sets any one of the interruption priority signal or the start priority signal in the circuit 4a or 4b to process the selected signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an input/output control device that controls the flow of data between a plurality of central processing units and a plurality of input/output devices, and particularly relates to an input/output control device that controls the flow of data between a plurality of central processing units and a plurality of input/output devices. The present invention relates to an input/output control device that optimally controls a start signal.

Generally, in modern computer systems, a central processing unit (hereinafter referred to as CPU) checks whether an external asynchronous event has occurred every time each program instruction is executed, and if no external asynchronous event has occurred. An interrupt mechanism is provided that executes the next instruction according to the logic of the program and transfers control to a specific address if 2 occurs.

Interrupt control is normally performed when an interrupt cause occurs.

This causes a strong transfer of control that is different from the progress of the program's logic, that is, transfer of control to a high-priority control program.

However, depending on the content of the interrupt cause, not all interrupts are necessarily of high priority.1 For example, an interrupt to report the end of a program instruction to the CPU, etc. There are some that perform h11-inclusive control.

On the other hand, as computer systems become faster and larger, CPUs with fast calculation speeds are developed and put into practical use, and when these are combined into a complex computer system, CPLLs with fast calculation speeds and CPUs with relatively slow calculation speeds This results in an extreme imbalance in instruction processing time with the CPU.

When performing interrupt control in such a system, there is a demand for the development of an input/output control device that corrects these imbalances and performs optimized interrupt control.

[Conventional technology]

FIG. 3 shows a block diagram of a compound computer system that performs multiple processing.

In the system shown in FIG. 3, for example, a plurality of input/output devices 38 to 3n (hereinafter referred to as 10[] 3a to 3n)
Hypernym for? W]a (For example, to execute the input/output command command from CPll> via path 2a, and to send the real machine completion report to the 10th device 1a,
When the input/output control device 2 (hereinafter referred to as 10C2) processes status interrupts from 03a to 3n, for example 1003a, conventionally, the following two methods are used to process the status interrupts.

That is, the interrupt status from l0D3a is
When output to the via interrupt instruction circuit 7 and the activation priority instruction circuit 8, the activation priority instruction circuit 8 outputs a preset signal 51.
=1 (activation priority signal) is output to the activation determination circuit 4a of the path 2a.

At the same time, the interrupt instruction circuit 7 sends an interrupt instruction signal to the 9-interrupt generation circuit 5a and the activation determination circuit 4b, and the 1-interrupt generation circuit 5a sends a request-in (2) to the host device 1a, and the activation determination circuit 4b sends an interrupt instruction signal to the host device 1b. for l0C2
In use ■' is reported and 1 interrupt processing is executed.

(1, 1: After l, key 1 interrupt status occurs, if the host device 1b continues to activate the path 2b, l0C2 will determine that the signal output to the activation determination circuit 4a is 81=1. Since this is a signal that gives priority to startup, the processing of request in ■ is put on standby, and startup ■′
processing is given priority.

(2) On the other hand, when the signal preset in the activation priority instruction circuit 8 is 31=O (interrupt priority signal).

When the host device 1b issues a startup ■', the signal output to the activation determination circuit 4a of l0C2 is 81-0, so the activation determination circuit 4h outputs l0C2 in use ■', and at the same time the interrupt generation circuit Prioritize processing of request in from 5a.

[Problem that the invention seeks to solve]

In the above-mentioned two examples of conventional methods, in the case of processing using method (1), in the complex system shown in FIG. - If the frequency of input/output commands from the host device 1b is too high, the input/output commands from the host device 1b are always processed with priority.

A case may occur in which the interrupt status processing for the device W 1 a does not proceed.

Furthermore, when processing using the method (2), there were problems such as the culm not progressing as expected due to multiple processing.

[Means for solving problems]

An object of the present invention is to realize a novel input/output control device that solves the above problems.

The problem is solved by providing a priority selection means for preferentially selecting the activation priority means and the interrupt priority means, and controlling the flow of data between the plurality of host devices and the plurality of input/output devices by the priority selection means. This problem is solved by the input/output control device according to the present invention.

[Effect]

That is, when the input/output control device holds the interrupt status from a predetermined input/output device, either a means for prioritizing the activation of the input/output device by an input/output command from a host device or a means for prioritizing 9 interrupts is selected. Using a startup/interrupt priority selection circuit that prioritizes selection at predetermined intervals, performs optimal status interrupt processing when the input/output control device is shared by a complex system, making the processing capacity of the complex system more efficient and appropriate. I tried to do this.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2.

FIG. 1 shows a complex system having an input/output control device according to the present invention, (A) is a block diagram of the complex system, (B) is an embodiment of the activation/interrupt priority selection circuit according to the present invention, and (C) is a block diagram of the complex system. 2 shows a time chart of the priority selection circuit according to the present invention, and FIG. 2 shows a flowchart of the input/output control device according to the present invention. The same symbols indicate the same objects or contents throughout the figures.

T1 shown in FIGS. 1(B) and (C) indicates the interrupt priority signal 51-0 output section, and T2 indicates the activation priority signal 51=
1 output section is shown. Further, it is assumed that the ratio between the T1 output section and the 12 output section is not a constant ratio, but cycles within a range of about 1:1 to 1:10 with a constant fluctuation cycle.

Note that TO in FIG. 1(B) is a clock signal generated in l0C2, and the numerical values in FIG. 1(C) indicate an example of the ratio between the Tl output section and the 12 output section.1For example, the first ratio is It is assumed that the 1:52 order is sequentially circulated as 1:6 and 1:7.

The activation/interrupt priority selection circuit 9 operates as follows. That is, a ratio signal that is sequentially circulated from the output signal of the counter 10 is created by the logic array 11.

The decoder 12 outputs this output as a 1I signal and a T2 signal to activation determination circuits 4a and 4b.

Next, this embodiment will be explained based on the flow chart of FIG.

In FIG. 2, the (al area) is the operating area of the activation/interrupt priority selection circuit 9, and the (b) area is the activation discrimination circuit 4a, 4b +
Operating area of interrupt generation circuits 5a and 5b, (C) is l0C
2 sets in use, (d) is the interrupt acceptance sequence, (
e) shows the activation acceptance sequence.

(ST-1): For example, l0D3a to l0C
When an interrupt signal is generated for 2, the control unit 6 activates/
Interruption (Check whether the state of the priority selection circuit 9 is in the Tl output section or the T2 output section.

(ST -2) : If it is the Tl output section, (ST
Go to -3>.

If it is the 12 output section, proceed to (ST-6).

(sr −3): Pass Tl signal and interrupt signal 2
a (In the case of an interrupt to the host device 1a) Set in the self-start discrimination circuit 4a.

If there is an activation ■' for l0C2 from a path other than the path 2a, the 1 interrupt instruction circuit 7 causes the activation determination circuit 4b to display that 1Oc2 is in use, and rejects the activation ■'.

(ST-4): Path 2a with interrupt signal set
If there is a startup from a path other than the path (such as path 2b), I O
Set C2 in use and move on to the next operation if there is no activation from another path.

(ST-5): Execute one interrupt sequence fd+ by instructing the interrupt generation circuit 5a to start.

(ST-6): Pass T2 signal and interrupt signal to 2
A is sent to the start-up determination circuit 4a.

Note that if there is activation to a path other than path 2a, activation can be accepted.

(ST-7): Path 2a with interrupt signal set
If there is activation from a path other than path 2b (such as path 2b), execute the activation acceptance sequence (e+), and if there is no activation from any path other than path 2a, proceed to the next step.

(ST-8): Execute one interrupt sequence (dl) by instructing the interrupt generation circuit 5a to start.

〔Effect of the invention〕

According to the present invention as described above, when the input/output control device is shared by a complex system, the interrupt processing of the input/output control device is appropriately proportioned in accordance with the system, and input/output commands to the input/output device can be smoothly processed. It has the effect of saying.

[Brief explanation of drawings]

FIG. 1 shows a complex system having an input/output control device according to the present invention, (A) is a block diagram of the complex system, (B) is an embodiment of the activation/interrupt priority selection circuit according to the present invention, and (C) is a block diagram of the complex system. 1 is a time chart of a priority selection circuit according to the present invention. FIG. 2 is a flowchart of the input/output control device according to the present invention. Figure 3 is a block diagram of a multi-processing computer system. are shown respectively. In fig. la and lb are upper-level devices, and 2 is roc. 2a and 2b are passes, 3a to 3n are l0I)
. 4a and 4b are activation determination circuits; 5a and 5b are interrupt generation circuits. 6 is a control unit. 7 is an interrupt instruction circuit, and 8 is a startup priority instruction circuit. 9 is a startup/interrupt priority selection circuit. 10 is a counter, 11 is logic, a logical array. 12 is a decoder, and 13 is an inverter. are shown respectively.

Claims (1)

[Claims] A startup priority system that is located between multiple host devices and multiple input/output devices, and even when the interrupt status for one of the host devices is maintained, priority is given to accepting input/output commands from the other host device. and interrupt priority means for waiting the input/output command processing until the interrupt status is processed when the interrupt status is held, in which the activation priority means and the interrupt priority means are selected preferentially. An input/output control device comprising a priority selection means, and the priority selection means controls the flow of data between the plurality of host devices and the plurality of input/output devices.