JPS6180352A - Multiprocessor control system - Google Patents

Abstract

PURPOSE:To improve the efficiency of processing by executing the release of the bus using right of a certain processor and the presentation of the bus using right of a processor having the highest priority at the same timing. CONSTITUTION:If a processor 2 sends a bus using request RO2 signal when a processor 1 is using the bus, a flip-flop (FF) 9 is set after one period of a clock. An output Q of the set FF 9 is sent to a memory control circuit through an OR circuit 13 and an output 'Q' is sent to a driver 4. The driver 4 opens an address gate and the processor 2 sends the address to a memory control circuit. The memory control circuit sends a response signal to FFs 8, 9, so that the FF 9 is rest and the processor 2 completes its operation at the bus cycle of 4 periods.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus that uses a plurality of processors to execute a job. The present invention relates to a multiprocessor control method that can quickly perform switching.

In recent years, with the spread of various information processing devices controlled by processors, devices that use a multi-processor 1ill 1M11 system that uses multiple processor trees and each processor independently performs processing once in a while. has appeared.

In this case, each processor shares the bus, so in order to increase processing efficiency, the processor using the bus passes the address control block to the processor of phase f after using the bus.
71 Luz Deco-1” needs to be performed quickly.

[Conventional technology]

FIG. 4 is a diagram illustrating a conventional multiprocessor control system, and FIG. 5 is a time chart illustrating the operation of FIG. 4.

When the processor 1 attempts to access, for example, the memory 6 via the bus 7, it sends out an RQI signal requesting the use of the bus 7, as shown in FIG. At this time, if processor 2 with higher priority does not send the use request RQ 2 signal, NOT
The output of the circuit 12 is "1", and since JI<flip-flop 9 is not set to 1, the ζ terminal is sending out "1". Therefore, the A N D circuit 10 sends out "1" and sets the JK flip-flop 8 after 1.tau. of the clock.

The output of the flip-flop 8 is sent as a P signal from the Q terminal to the memory control circuit 5 via the OR circuit 13, and the output signal is sent to the memory control circuit 5 as a Gl signal from the output terminal.
゛ is sent at l'' time 3.

Since the driver 3 opens the address gate 1 when receiving the *G1 signal iJ of 0, the processor 1 can use the bus 7 and sends an alarm to the memory control circuit 5. In addition, the memory control circuit 5 controls the memory control circuit 5 by the P signal.
After decoding the response, the RAS (word selection) is stored in memory 6.
The memory control circuit 5, which sends out the RAS signal and the CAS (digit selection) signal, sends out the response signal ANS to the K terminals of the flip-flops 8 and 90) after the RAS signal output clock τ. Therefore, flip-flop 8 is set and *G
1 signal is restored.

Assume that processor 2 sends a bus 7 use request signal RQ2 while processor I is using bus 7.

When the flip-flop 8 is turned on and the Q terminal becomes 1, the AAND circuit 11 sends out 1, and the flip-flop 1:1 block 9 is set 1τ after the clock.

The set Frisobuf 1': I knob 9 sends "1" as a signal from the Q can and i end to the memory control wholesale circuit 5 via the OR circuit 13, and also sends "0" as the *G2 signal from the end end.゛ is sent to the driver 4.

Driver 4 is "0゛*c 2 (receives g and addresses ')"t・'? c open < for, processo 92
becomes able to use the bus 7 and sends an address to the memory control circuit 5. Further, the memory control circuit 5 sends the RAS signal and the C'' and AS signals to the memory 6 after the decoding of the AIL and S is completed based on the I] times signal.

Memory control rotation 5 is 2τ of the clock after sending the RAS signal.
Afterwards) the response signal ΔNS is sent to terminals 8 and 9 of the flinopf 11. Therefore flip flop! ], the *G2 signal is restored.

Next, when a request to use the processor 1 or the bus 7 is sent, the processor 1 operates in the same manner as described above, following the operation of the processor 4J2.

[Problem that the invention seeks to solve]

When operating in a multi-processor system, each processor performs independent processing, and after the first processor finishes using the bus and before the next request occurs, it returns the state it was in 1) until then. The second Broceso IY often starts using the bus.

By the way, since the conventional multiprocessor control circuit operates as described above, each processor generates a bus use request and then opens the address game 1 to use the bus, which requires a bus cycle time of 5τ for each processor. However, even though processor 2 sends a bus use request while the processor is using the bus, it has to wait for 7 trace cycles of the driver, resulting in poor efficiency. be.

[Means for solving problems]

The problem described in item 2 is that in a system A where multiple processors operate by occupying a shared bus alternately, when the processor finishes using the bus, if another processor is requesting the use of the bus, the above problem occurs. A book that makes it possible to abandon bus use 1t[ of a certain proceso 4J- and administer bus use Ik to Browlenosa, which has the highest priority among those requesting bus use, at the same time. The problem is solved by the multiprocessor control method according to the invention.

[Effect]

In other words, when multiple processor buses are used, generally after the first processor accesses, the second processor often accesses the bus, so each processor
After the request is completed, the processor's request for access with a higher priority is suspended.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart 1 for explaining the mJ+ operation of FIG. 1.

Figure 1 is an AND circuit of 15.17 and 01? in the circuit of Figure 4.
Circuit 14, LFI with powerful 11 shi, others are 4th
It is the same as the figure, and the bus 7, memory control circuit 5, and memory 6 are omitted.

Processor 1 receives bus usage request RQI as shown in FIG.
Send out faith. At this time, if the processor 2 with the old priority level 1 does not send out the use request RQ2 signal, the NOT circuit 1
The output of 2 is ``'1pa'' and 1.JK Flimp Flossop 9
Since it is not set, the mouth terminal is sending out "" 1pa. Therefore, the ANr) circuit 10 sends out "1",
After passing through the OR circuit 14 and 1τ after the clock, the JK flip-flop 8 is set.

Seven so! - Sends l' as the flip-flop P signal to the memory control circuit via the OR circuit 13, and sends '0' to the driver 3 as the *G1 signal from the terminal.

When the driver 3 receives the *Gl signal, it opens the address gate and sends the address to the processor I4;t: memory control circuit. In addition, the memory control circuit receives the P signal.
1; 1 A
and CAS signals. Memory control circuit I≧A
After the S signal transmission signal is sent out, a response signal -ΔNS is output to the terminals of flip-flops 8 and 9. Therefore, flip-flop 8 is set and the *G1 signal is restored.

Assume that processor 1 of bus processor 1 processes the bus while processor 1 is using the bus, and processor 2 sends a bus use request R02 signal. Flip-flop 9 is not set, so the C terminal is "I"
When the response signal ΔNS is input, the AND circuit 17 performs the OR
via the circuit 16 to the Flinopf 11 knob 9. Therefore, the flip-flop 9 outputs p after 1τ of the clock.
Get throated. Therefore, the *G2 signal is sent out following the *G1 signal.

If you are a hit person, you will receive 130% of all 13 terminals.
At the same time, the σ terminal *G2 is sent to the memory control circuit.
It sends the signal to the driver 4 as a signal. As mentioned above, when the flip-flop 8 is turned 1, the edge -r becomes "B", and the driver 2 sends the RQ 2 signal to the driver 4. Since ANr) circuit IN; sends out 1', flip-flop 1] is already ・I!, so this I υiJyjjj f is seen.

When driver 4 receives the *G2 Shingetsu signal, it opens Atres 1, and processor 2 sends an pulse to the memory control circuit. Further, the memory control circuit transmits the RAS signal and the C signal to the memory after the address has been decoded by the P signal.
Sends an AS signal. After the RAS signal output clock τ, the memory control circuit sends the response signal ANS to the (11) terminals of the flip-flops 8 and 9. Therefore, the flip-flop 9 is reset, and the *G2 signal is restored and the processor 2 The operation can be completed with a bus cycle of 4τ.

Assume that processor 2 sends a bus use request RQI signal while processor 2 is using the bus. Since the flip-flop 9 is set, the C terminal - is "o" and the AND circuit 1o does not operate.

Since the flip-flop 8 is connected to the reset circuit 1, the output terminal is "1". Therefore, when the response signal ANS is input, ANr
) circuit 15 sends "1" to flip-flop 8 via OR circuit 14. Therefore, flip-flop 8 receives 1.tau.1 of the clock.

Therefore, the *G2 signal B was followed by the *G1 signal, and the seven I/Frisobuff +1 knobs 8 were the P signal 74 from the mouth terminal.
ToL7 "I"oR1i'! While sending the circuit 13 to the memory control circuit, page ◇J. 1 finished*G
Sends "0pa to 1u/Iha3 as a 1 signal.

Therefore, when Tetricha 3 receives the *G1 signal, it opens address 5-1, and P11's IJ1 sends a 71 pulse to the memory control circuit.
) signal, when the address is decoded, the R A S signal and the CAS signal are sent to the memory.

The memory control circuit sends a response signal ANS to the terminals of flip-flops 8 and 9 2τ after sending the RAS signal 7j. Therefore, the Tsurinob flop 8 is seven throated,
*G1 Shingetsu signal is old, proscenology 1 4; l: 4
The operation can be completed by bus recycle of r.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, in which the process,
4) is composed of a plurality of 3 1 pu L:.

Figure 3 shows a state in which the i-th [1] processor opens the address gate of the driver in a synutem consisting of 1711 processors.The higher the number, the greater the priority.This condition Processor 1 does not occupy the bus, and processor i has sent a bus use request. This is possible because the response signal ANS has arrived at a processor other than the processor.

AND circuits 20 and 22 receive a request to use processor i RQi
A signal comes in. At this time, the IK flip-flop 24 is not set, so the ζ terminal is sending out "1".

The output of the AND circuit 21 is "1" since the *RQi+1 to *RQn signals are "1" if the processor 1 "-1 to -1- processor has not sent a usage request.
It is. Therefore, when the response signal ANS is input, the ANT) circuit 2
2 is "1" through the OR circuit 23 and the flip-flop 24.
The flip-flop 24 is set after 1τ of the clock.

The flip-flop 24 which has been set to 1 has a Q terminal.
＋P
``o'' is sent from the cap i Y- as a *Gi signal at l time.

If one or more processes y+ have sent usage requests, *R(l i l l -* R
Since one of Qn is "o", AND circuit 21
The output of ``' (1) is 8N l-) circuit 20.
22 co-operation - loss, flip-flop 24 or hino 1 - not activated.

Therefore, the signal *O1 that opens 1-1-1
is not sent.

Also, if the processors or buses from 1 to 1 to i-1 are in use, then any one of l-G i-1 becomes 0', AND Since the circuit 20 does not operate and the A N D circuit 22 does not operate until NS comes to the response signal, the flip-flop 24 is not turned on, and the 71'-Leslie 1 is not opened even after 1 circuit. It does not harm the operation of other processors.

〔Effect of the invention〕

As described above, the present invention enables continuous switching of Atreske and improves processing efficiency in multiprocessor control.

[Brief explanation of drawings]

Fig. 1 is a professional diagram of a circuit showing one embodiment of the present invention, Fig. 2 is a time chart 1 explaining the operation of Fig. 1, and Fig. 3 is a circuit showing another embodiment of the present invention. 4 is a diagram explaining a conventional multiprocessor control circuit, and FIG. 5 is a time chart (-) explaining the operation of FIG. 4. In the figure, 1.2 is a processor, 3 and 4 are l - time, 5 is a memory control circuit, 6 is a memory, 7 is a bus, 8.9.24 is a JK flip-flop.

Claims (1)

[Claims] In a device in which a plurality of processors operate by alternately occupying a shared bus, when a certain processor finishes using the bus and another processor requests the use of the bus, the certain processor relinquishes the right to use the bus. A multiprocessor control method is characterized in that the bus use right is granted to the processor with the highest priority among those requesting bus use at the same timing.