JPS6180464A - Operator for variable density image - Google Patents

Abstract

PURPOSE:To attain the product/sum operation and the conversion of density in parallel to each other for an input image, by storing previously a coefficient for the product/sum operation and a conversion table for conversion of density into a memory and extracting these stored data when necessary. CONSTITUTION:A memory 21 stores a coefficient for product/sum operation and a conversion table for conversion of density. When the input image data A is supplied to the memory 21, the data A is multiplied by the coefficient. The value of this multiplication is supplied to an arithmetic logical operation unit 23 and added with the input image data B. Thus data f(A)+B is delivered. For the conversion of density, the memory 21 selects a page storing a density conversion table corresponding to the input image data by a command given from a page designating register 22. Then only the data f(A) is delivered from the unit 23 via a function designating register 234 when the data A is supplied to the memory 21. Thus both the product/sum operation and the conversion of density can be carried out in parallel to each other by storing a density conversion table, etc. into the memory 21.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a grayscale image calculator in an image processing device.

(Prior art) In the digital processing of a light and light image in an image processing device, the sum of products and density conversion of image data are performed using basic 1
It is Noh. FIG. 5 is a block diagram showing an example of a conventional product-sum calculation circuit. This product-sum operation circuit is a high-speed parallel
The multiplier 1 of the form inputs the first image data 8, and the coefficient setter 2 sets the constant rj1. Then, in the arithmetic and logic unit 3, the sum of -A and the second image data B is added to the output of the multiplier 1, and the result is (
K・A+B) is output as image side data. The signal line in the figure is, for example, an 8-bit bus. The number 11BIT in the figure indicates the number of bits (the same applies below). The arithmetic and logic unit <ALU) 3 is operating as an adder in this case.

FIG. 6 is a block diagram showing an example of a conventional density conversion circuit. (a) shows the case where it is placed in the input section, and (b) shows the case where it is placed in the playback section. The image signal sent from the television camera is sent to the video input circuit 11.
After signal processing such as amplification is performed in the A/Da converter 12, the signal is converted into, for example, 8-bit digital data. Note that the video input circuit 11 and the A/D converter 12 constitute an input image processing circuit 10. The output of the A/D converter 12 is given to the memory 13 as an address. memory 1
3 stores density conversion data corresponding to input image data in a fixed functional relationship. When an address is given to the memory 13, the density conversion data (8 bits) stored at the address corresponding to the address is output.

When reproducing an image from once-converted data, the procedure is as follows. The density conversion data output from the memory 13 is D
, 'A converter 14 converts the signal into an analog signal. This analog signal is subjected to signal processing such as amplification in the subsequent video output circuit 15. Note that the D/Δ converter 14 and the video output circuit 15 constitute an output image processing circuit 20.

The output of the video output circuit 15 is reproduced and displayed on a display such as a television.

(Problems to be Solved by the Invention) As described above, in the conventional example, the product-sum calculation circuit and the temperature conversion circuit are provided separately and independently, which makes the configuration of the image processing device complicated. It had become.

The present invention has been made in view of these points, and
The purpose is to realize a density image calculator that can perform both product-sum calculation and density conversion of an input image.

(Means for Solving the Problems) The present invention for solving the problems described above first includes a memory that receives a first input image signal as an input and stores a functional relationship corresponding to the input; and an arithmetic and logic operation unit that performs 'e4 arithmetic in response to the output of the image signal and the second input image signal, and is characterized in that the output of the arithmetic and logic operation unit is used as its output. It is composed of a memory that receives a first input image signal as an input and stores a functional relationship corresponding to the input, and an arithmetic and logic operation unit that receives the output of the memory and a second input image signal and performs 11 operations. The present invention is characterized in that v1 pieces of a and light image calculation circuits are connected in series, and the output of the gray and light image calculation circuit is the output of the gray and light image processing circuit of the final connected stage.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, numeral 21 is a memory in which coefficients and density conversion tables used during product-sum calculations are stored as functional relationships with respect to image input.

First input image data is given to the memory 21 as an address. The menu 21 is composed of a plurality of pages, and the page specification is made using the page specification register 22.
This is done by As the memory 21, for example, LUT (L
ook Up Table) is used. As the memory, for example, ROM or RAM is used. 2
3 is an arithmetic and logic unit (ALU) which receives the output data of the memory 21 at its p input and the second input image data at its q input and performs each operation process.The arithmetic and logic unit 23 includes: For example, an 8-bit ALU that combines two ALUs of 41; The output becomes output image data.Memory 21.
The page designation register 22.degree. arithmetic logic operation unit 23 and function designation register 24 constitute a gray scale image calculation unit 30 according to the present invention. The operation of the circuit configured as described above will be explained as follows.

First, a case will be described in which a sum-of-products operation is performed using the circuit shown in the figure. In the memory 21, a page in which a coefficient conversion table corresponding to input image data is stored is selected by a command from a page designation register 22. FIG. 2 is a diagram showing the states of functions stored in the memory 21.

In the figure, (a) shows the case of product-sum calculation, and (b) shows the case of density conversion. In the case of the product-sum operation, conversion data is stored in the memory 21 in the form of the function shown in (a). That is, inputs and outputs are stored in the form of linear functions. Note that A and LU functions in the figure indicate the functions of the numbing logic operation unit 23 in each case of product-sum operation or concentration conversion. memory 2
1, when the first input image data A is input, the memory 21 outputs the conversion data "(A)" corresponding to the input.Currently, the memory 21 has selected the coefficient conversion table, so its output f (A) becomes la K - A, which is input A multiplied by coefficient K. This conversion data " (△) is
The logic operation unit 23 is entered. The logic operation unit 23 is set by the function designation register 24 to operate as an adder. Therefore, the converted data f (A) entered into the arithmetic logic unit 23
is added to the second input image data B, and the addition result f(
A>+8 is output from the arithmetic and logic unit 23 as image data. The extracted image data is, for example, CR
It is reproduced as an image on T.

Next, a case will be described in which density conversion is performed using the circuit shown in the figure. In the memory 21, a page in which a density conversion table corresponding to input image data is stored is selected by a command from a page designation register 22. In the case of density conversion, conversion data is stored in the memory 21 in the form of a nonlinear function as shown in FIG. 2 (b). When the first input image data A is input to the memory 21, the memory 21
outputs density conversion data f (A> corresponding to the input. This density conversion data f (A> enters the arithmetic and logic operation unit 23. Now, the arithmetic and logic operation unit 23
is specified in the memory 2 by the function specification register 24.
It is configured to act as a multiplexer, passing only the data from 1 and blocking the passage of the second input image data. Therefore, from the arithmetic and logic operation unit 23, only the density conversion data "(A)" in the memory 21 is output as image data.The extracted image data is used as an image on a CRT, for example, as in the case of the product-sum operation. As described above, according to the present invention, by specifying the pages of the memory 21 and the functions of the arithmetic and logic unit 23 from their respective designated registers, it is possible to perform both the product-sum operation and the concentration conversion function. You can make it happen.

In the above description, the configuration is shown in which the arithmetic precision is 8 bits and a 168i conversion function can be selected as the memory 21. can be used in combination with a 4-bit ALU of 2 wA. Further, in the above description, the calculation precision is 8 bits, but it is not necessary to limit it to 8 bits. When more precision is required in product-sum calculations such as local filtering, if the hardware of the memory 21 and arithmetic and logic unit 23 is designed for twice the 16-bit operation as shown in Figure 3, the calculation R degree can be reduced. Improved by 2 times. In addition to specifying the page of the memory 21 with a register and fixing the multiplication coefficient, as shown in the figure, image data giving a multiplication coefficient can be used for page specification, and the coefficient can be specified with a video rate. The data may be multiplied by σ.

FIG. 4 is a configuration block diagram showing another embodiment of the present invention. The circuit shown in the figure is constructed by connecting 3111 grayscale image arithmetic units shown in FIG. 1 in series through a vibe line. 1st
The gradation image calculation unit 100 in the third stage has a multilevel vibe line register (Multilevel) that receives an R (red) signal of the color video signal as image data.
Pipeline Register (hereinafter simply referred to as MPR)110. A memory 1201 receives the output of the MPR 110, an arithmetic and logic unit 130 receives the converted output data and constants of the memory 120, and a register 140 receives the output of the arithmetic and logic unit 130.

The second-stage grayscale image calculator 200 is an MPR that receives a G (green) signal of the color video signal as image data.
210, a memory 220 that receives the output of the MPR 210;
an arithmetic and logic operation unit 23 that receives the conversion output data of the ffl memory 220 and the output of the first grayscale image operation unit 100;
0 and a register 240 that receives the output of the arithmetic and logic operation unit 230, and the third stage gray scale image calculation unit 3○O receives an MPR 310 that receives the B (blue) signal of the color video signal as image data. ,RM PR31
a memory 320 that receives an output of 0, a logic logic unit 330 that receives the converted output data of the memory 320 and the output of the second gray scale calculator 200, and a register 340 that receives the output of the arithmetic logic block unit 330. It consists of

The MPR 110 of the first i-light image calculator 100 has a one-stage configuration, and the second 'a-light image calculator 200 MPR 210 has a two-stage configuration.
In the stage configuration, the MPR 310 of the third gray scale image calculation unit 300
Each has a three-stage configuration. Each of these MPRs is
This is a group of registers that corrects distortion caused by data delays, and the number of shift stages can be changed by programming. Further, the registers 140, 240, and 340 absorb data delays caused by data transfer between the a-frame image processing units.

In the circuit configured in this manner, the operation of each grayscale image calculator is the same as that shown in FIG. 1, and therefore a description thereof will be omitted. Now, if the image data is R, the coefficient of the memory 120 is r, and the constant is th, then the output of the first stage is th+r-R. Next, if the image data of the second stage is G and the coefficient of the memory 220 is 9, the output of the second stage is h+r-R+g-
It becomes G. Next, if the image data of the third stage is 8 and the coefficient of the memory 32o is b, the output of the third stage is th+r-R+a
・G+b-8<1). That is, the circuit shown in the figure can perform a linear operation n as expressed by equation (1) on a color image of 83 colors, R and G. Note that the number of connected stages does not need to be limited to three, and may be any number.

(Effects of the Invention) As described above in detail, according to the present invention, coefficients for product-sum calculations and conversion tables for density conversion are stored in advance in the memory, and are stored as necessary. By extracting data, it is possible to realize a grayscale image calculator that can perform both product-sum calculation and density conversion of an input image. Furthermore, by connecting multiple stages of this circuit in series with a vibration line? ! Linear enclosing can also be performed on color images of several colors. Also according to the invention! ! Since it is composed of a light image arithmetic unit memory and an arithmetic and logic operation unit, operations other than multiplication (absolute value, square, etc.) can be performed by changing the contents of the memory, increasing the operation + i capability.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
3 and 4 are block diagrams showing other embodiments of the present invention, FIG. 5 is a diagram showing a conventional example of a product-sum operation circuit, and FIG. (This is a diagram showing a conventional example of a fold degree conversion circuit. 1... Multiplier 2... Coefficient setter 3.23
,130,230.330...Arithmetic logic unit 10...Input image processing circuit 11...Video input circuit 12...Δ/D conversion circuit 13.21.120.220,230-...Memo 1J1
4...D/Δ converter 15...Video output circuit 20
...Output image processing circuit 22...Page 1 designation register 24...Function designation register 30.100,
200, 300... Grayscale image calculator

Claims (2)

[Claims] (1) A memory that receives a first input image signal as an input and stores a functional relationship corresponding to the input, and an arithmetic logic unit that receives the output of the memory and a second input image signal and performs an operation. A gray scale image computing unit configured to have an output of the arithmetic and logic unit as its output. (2) a memory that receives a first input image signal as an input and stores a functional relationship corresponding to the input; and an arithmetic and logic operation unit that receives an output of the memory and a second input image signal and performs an operation. A grayscale image calculation unit in which a plurality of the configured grayscale image calculation circuits are connected in series via registers, and the output of the grayscale image calculation circuit at the final connected stage is used as the output.