JPS6180593A - Dynamic RAM - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a dynamic RAM, and, for example, to a technique effective for a dynamic RAM with a large storage capacity.

[Background technology]

1-bit memory cell M in dynamic RAM
C is an information storage capacitor Cs and an address selection MOS
FETQm, and information on logic "1" and "υ' is stored in the form of whether or not there is charge in the capacitor Cs.

To read and output information, turn on the r~40SFETQm, connect the capacitor C3 to the common data line DL, and check how the potential of the data line DL changes depending on the amount of charge accumulated in the capacitor Cs. This is done by sensing what happens.

The memory cells MC are formed small and the common data line D
Since many memory cells are connected to L to form a highly integrated and large capacity memory matrix, the capacitor Cs and
The relationship between the common data line DL and the stray capacitance Go is C3/
The Co ratio becomes a very small value. Therefore, about 1M
In the development of dynamic RAM with a storage capacity of bits, the elements constituting the memory cell are miniaturized, so the C3/Co ratio mentioned above becomes smaller and smaller, making it difficult to increase the storage capacity. It's becoming a bottleneck.

Therefore, as a result of studying the stray capacitance of the data line, the inventor of the present application has determined that the common data line DL can be connected to the common data line DL by circuit means.
It has been found that the capacitance value of the floating capacitance fCo can be reduced. For the dynamic RAM, see, for example, Japanese Unexamined Patent Publication No. 74535/1983.

[Purpose of the invention]

An object of the present invention is to achieve high-speed read operation of a dynamic RAM with a large storage capacity and high-speed operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by connecting an active restore circuit that is not related to the operating speed to the data line through a switch MOSFET among the circuits that constitute the stray capacitance Co of the data line, the stray capacitance in the active restore circuit is separated from the data line. It is intended to do so.

〔Example〕

FIG. 1 shows a configuration diagram of an embodiment of a memory array in a dynamic RAM according to the present invention.

In this embodiment, although not particularly limited, a pair of memory arrays M-ARY1. A unit memory array is configured by M-ARY2. That is, each memory array M-
ARY1. M-ARY2 is a sense amplifier SA.
I, SA2 and precharge circuits PCI, PC2 are provided. In addition, both the memory arrays M-ARYI, M-A
An active restore circuit AR is arranged between RY2. In this way, a pair of memory arrays M-ARYI.

Active restore circuit A common to M-ARY2
R is provided in each memory array M-ARYl, M-A
This is intended to reduce the stray capacitance of the data line in RY2 and to simplify the circuit. Note that the active restore circuit AR includes a switch MOSFE as described later.
T through each memory array M-ARY1. M-ARY2
It is selectively connected to the data line.

FIG. 2 shows a circuit diagram of one embodiment of each circuit of one memory array M-ARYI. In the figure, a pair of complementary data lines DL forming memory array M-ARYI are shown.
, DL are illustrated as representative circuits.

In the example circuit shown in the figure, an n-channel MOSFE
I G F E T (I n5ula
tedCrate Fteld Effect Tr
Ansistor) will be explained as an example.

A 1-bit memory cell MC has an information storage capacitor Cs and an address selection M as shown in FIG.
O3FE'l'Qm, and information of logic "1" and "0" is stored in the form of whether the capacitor Cs has a charge or not.

To read information, turn on MOSFETQm and connect capacitor C! 3 to a common data line DI, and senses how the potential of the data line DL changes depending on the amount of charge multiplied by M in the capacitor Cs.

The memory cells MC are formed small and the common data line D
Since many memory cells are connected to L to form a highly integrated and large capacity memory matrix, the capacitor Cs and
Regarding the relationship between the common data line LIL and the floating capacitance 1ico, the ratio of Cs/Co becomes a very small value. Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs is a very small signal.

In order to detect such a minute signal, a dummy cell (not shown) is provided to form a read reference voltage, although this is not particularly limited. This dummy cell is made under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitor is approximately half the size of the dummy cell, although this is not particularly limited. The dummy cell capacitor is charged to ground potential prior to addressing.

As mentioned above, since the capacitor of the dummy cell is set to approximately half the capacitance value of the capacitor Cs of the memory cell MC, the read signal from the memory cell MC forms a read reference voltage equal to half y'. become.

In the same figure, SAI is a sense amplifier that expands the difference in potential change caused by the above-mentioned addressing into a sensing period determined by a timing signal (sense amplifier control signal) φpa (its operation will be described later). Its input/output nodes are coupled to complementary data lines DL, DL arranged in parallel. The number of memory cells coupled to the complementary data lines DL, DL is made equal to increase detection accuracy, and one (1) dummy cell is coupled to each of the complementary data lines DL, DL. It is coupled between one word line WL and one of the complementary pair of data lines.Since each word line WL crosses both data line pairs, noise components generated on the word line WL are coupled by capacitive coupling. Even on the data lines, the noise component appears equally on both data line pairs DL and DL, and the differential sense amplifier SAI
offset by.

In the above addressing, complementary data line pair DL, D
When a memory cell MC coupled to one of L is selected, one of a pair of dummy word lines is selected so that a dummy cell is always coupled to the other data line.

The sense amplifier SAI has a pair of cross-wired MO
SFETQ5. Q6, and due to their positive feedback action, the minute signals appearing on the complementary data lines DL, DL are differentially amplified. This positive feedback operation is performed by the timing signal φpa
It is started when MOS FETQ7 is turned on. In this case, as the above MOSFETQ7, 2
(7) It is desirable to perform this in two stages using MOSFETs.

In other words, M with relatively small conductance characteristics
The sense amplifier SA starts operating at the same time that the OS FET starts conducting due to a relatively fast timing signal, and the higher data line potential is changed at a slow speed based on the potential difference given to the complementary data lines DL and DL by addressing. , the lower one descends at a faster rate while the difference widens. Then, at the timing when the voltage difference becomes large to a certain extent, the MOSFETQ, which has a relatively large conductance characteristic, is made conductive by a delayed timing signal. This causes the lower data line potential to drop rapidly. By operating the sense amplifier SA in two stages in this manner, the drop in the higher potential is prevented. In this way, when the lower potential drops below the threshold voltage of the cross-coupled MOSFET, the positive feedback operation ends, and the drop in the higher potential is caused by the power supply voltage Vc
The voltage remains at a potential lower than c and higher than the threshold voltage, and the lower potential eventually reaches the ground potential (OV).

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, if the high level drops by more than a certain level with respect to the power supply voltage Vcc, a malfunction occurs in which the data is read as a logic "0" while reading and rewriting are repeated several times.

An active restore circuit AR is provided to prevent this malfunction. In this embodiment, in order to selectively use the corresponding complementary data lines DL, DL of the pair of memory arrays M-ARYI, M-ARY2, the switches MOSFETQ11. Q12 and Q13. Q1
4 to the complementary data lines DL, DL.

This active restore circuit AR has the function of selectively boosting only high level signals to the potential of power supply voltage Vcc without having any effect on low level signals.

Capacitor CB1. CB2 is an M whose capacitance changes depending on the potential from the data line applied to its gate.
It is an O3 type variable capacitance element, and it should be understood that, theoretically, a capacitor can be formed at a high applied voltage based on the threshold voltage, and a capacitor cannot be formed at a low voltage.

For example, one of the complementary data lines DL, DL of the memory array M-ARYI is set to 1f by the sense amplifier SA, 1.
1 (low level), MO controlled by the timing signal (active restore control signal) φreg
SFETQ2. Of Q4, only the MOS FET connected to the low level data line is turned on, and the MOSFET is turned on.
SFETQ1. Either gate voltage of Q3 is discharged to the same low level as the data line. Next, when the timing signal (active restore control signal) φres becomes high level, the MO belonging to the data line on the high level side
The gate potential of 9FETQI (or Q3) is the power supply voltage V
cc, the high level of the data line is restored to the Vcc level, and the stored information in the memory cell MC coupled to this data line is similarly restored to the high level (Vcc).

Note that when the memory array M-ARYl side is selected, the timing signal φ1 causes MOSFETQI 1
．． Ql 2 is turned on, and the memory array M-
Complementary data 1JjDL on the ARYi side.

An active restore circuit AR is connected to DL.

The timing signal φ1 is generated at the timing when the positive feedback amplification operation of the sense amplifier SAI is completed.

Further, when the memory array M-ARYZ side is selected, the timing signal φ2 causes MOSFETQ13.
Ql4 is turned on, and the memory array M-AR
Complementary data line DL on the YI side.

An active restore circuit AR is connected to DL.

The timing signal φ2 is generated at the timing when the positive feedback amplification operation of the sense amplifier SA2 is completed. In this way, memory array M-ARYI or M-AR
By selectively forming the timing signal φ1 or φ2 according to the memory cell Y2, the active restore circuit AR is selectively used. Incidentally, the sense amplifiers SAI and SA2 are selectively operated in the same manner as described above.

〔effect〕

(11 active restore circuit AR switch MOSF
By connecting to the data line via ET, the active restore circuit can be separated from the data line when reading the stored information of the memory cell to the data line. As a result, the capacitance value of the stray capacitance CO in the data line can be reduced, so that the ratio Cs/Co of the memory cell to the information storage capacitor Cs can be increased. As a result, it is possible to increase the actual reading level of the stored information, so that it is possible to obtain the effects of improving the operating margin and increasing the speed of operation.

(2) According to (11) above, since the capacitor Cs of the memory cell can be formed relatively small, the elements of the memory cell can be miniaturized, so that it is possible to achieve the effect of realizing a large storage capacity.

(3) By using the active restore circuit for a pair of memory arrays, it is possible to simplify the circuit.

(4) When the sense amplifier starts positive feedback operation, by separating the active restore circuit from the data line, the active restore circuit is operated only after the level of the data line becomes sufficiently large. As when the restore circuit is directly connected to the data line, the level of the timing signal φreg decreases as the power supply voltage Vcc decreases (bump), and the level of the timing signal φreg decreases to MOSFET Q2. Q4
is turned off and capacitor CBI (or CB2) continues to hold the previous high level, causing the data line to fall to the low level side when reading a minute voltage from the memory cell during the word line selection operation and when the sense amplifier operates. It is possible to prevent malfunctions due to deterioration of the condition.

(5) Active restore circuit switch MOSFET
Even if the active restore circuit is separated from the data line, it simply restores the dropped high level on the data line, and its operating time is not included in the read access time, achieving high-speed operation. The effect of being able to do this is obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the specific circuit of the active restore circuit can be modified in various ways. Further, the specific configuration of the memory array constituting the dynamic RAM and the configuration of its peripheral circuits can take various embodiments.

For example, there are 128 word lines and 1024 data lines.
A total of four memory arrays are arranged, two of which are
By sharing the active restore circuit between two memory arrays, a dynamic RAM having a total storage capacity of 1 Mbit can be constructed. moreover,
The active restore circuit may be provided for each memory array.

[Application field]

The present invention can be widely used in dynamic RAMs that require active restore operations.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of a memory array in a dynamic RAM according to the present invention, and FIG. 2 is a circuit diagram showing a specific embodiment thereof. M-ARYl, M-ARY2...Memory array, MC.
・Memory cell, SAI, SA2...Sense amplifier, AR
・・Active restore circuit, PCl, PO2 ・・Precharge circuit χ−<shiX~

Claims (1)

[Scope of Claims] 1. A plurality of memories each consisting of data lines and word lines arranged in a matrix, and an address selection MOSFET and an information storage capacitor, each provided at the intersection of the word line and data line. A memory cell, a sense amplifier that is directly connected to the data line and amplifies the stored information of the memory cell read to the data line, and an active restore circuit that is connected to the data line via a switch MOSFET. Dynamic RAM. 2. The dynamic RAM according to claim 1, wherein the data lines are a pair of complementary data lines arranged in parallel. 3. Claim 1 or 2, characterized in that the active restore circuit is disposed at an intermediate portion between a pair of memory arrays and is used selectively with respect to the pair of memory arrays. Dynamic RAM described in section
.