JPS6180824A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6180824A
JPS6180824A JP59202688A JP20268884A JPS6180824A JP S6180824 A JPS6180824 A JP S6180824A JP 59202688 A JP59202688 A JP 59202688A JP 20268884 A JP20268884 A JP 20268884A JP S6180824 A JPS6180824 A JP S6180824A
Authority
JP
Japan
Prior art keywords
photoresist
metal
exposed
etching
metals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59202688A
Other languages
Japanese (ja)
Inventor
Minoru Hori
堀 稔
Jiro Ida
次郎 井田
Tadashi Kinomura
木野村 正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP59202688A priority Critical patent/JPS6180824A/en
Publication of JPS6180824A publication Critical patent/JPS6180824A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To prevent generation of the short-circuit between metals such as Al and the like and the contact of the Al and the like and a metal etchant by a method wherein, after the metal such as Al and the like located on a photoresist is completely removed, the exposed photoresist is removed. CONSTITUTION:The pattern of a photoresist 2 is formed on a silicon substrate 1 using a photolithographic technique, and Al 3 is adhered on the whole surface by performing a vacuum evaporation method and the like. Subsequently, a photoresist film 4 is coated by performing a spin-on method and the like. Then, an etching is performed on the photoresist 4 until the surface of the Al 3 is exposed by performing a dry etching and the like using CF4 gas. The exposed Al 3 is etched using a phosphoric acid and the like, and lastly, the photoresists 2 and 4 are completely removed using a parting liquid and the like.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路等の半導体装置の製造方法、特に電極
などf二用いるアルミニクム′Jどのメタルのフォトリ
ソグラフィ技術によるバターニング方法に関するもので
ある。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing semiconductor devices such as integrated circuits, and in particular to a method for patterning aluminum or other metals using photolithography technology such as electrodes. .

〔従来の技術〕[Conventional technology]

従来、At等のメタルの微細バターニング方法として、
■リフトオフ法、■化学エッチ法が用いられている。こ
れらについて以下孟:説明する。
Conventionally, as a fine patterning method for metals such as At,
■Lift-off method, ■Chemical etch method are used. Meng will explain these below.

■リフトオフ法 第3図に示すようg:、シリコン基板1上に、フォトリ
ソグラフィ技術により、フォトレジスト2のパターンを
形成する(図A)。次C:、この上(:、真空蒸着法等
により、全面にAt等のメタル5を付着させる(図B)
。次に、レジストはくり液等により、フォトレジスト2
を除去し、同時にフォトレジスト膜上のAt等のメタル
3も除去する。
(2) Lift-off method As shown in FIG. 3, a pattern of photoresist 2 is formed on silicon substrate 1 by photolithography (FIG. A). Next C:, On this (:, Attach metal 5 such as At to the entire surface by vacuum evaporation method etc. (Figure B)
. Next, remove the photoresist 2 using a resist stripper or the like.
At the same time, metal 3 such as At on the photoresist film is also removed.

その結果、図CのようにAt等のメタル3が所望のパタ
ーンになっている。
As a result, the metal 3 such as At has a desired pattern as shown in FIG.

ところが、第4図のように、At等のメタル5がフォト
レジスト2を完全にカバーしてしまうことがあり、この
場合フォトレジスト膜がフォトレジストばくり液と接融
しないため、フォトレジスト2が完全(二除去できない
場合があり、At等メタル間でショートが生じ易い欠点
がある。
However, as shown in FIG. 4, the metal 5 such as At may completely cover the photoresist 2, and in this case, the photoresist film does not melt with the photoresist removal solution, so the photoresist 2 Complete removal may not be possible in some cases, and there is a drawback that short circuits tend to occur between metals such as At.

■化学エッチ法 第2図に示すように、まずシリコン基板1上(二全面に
真空蒸着法によりAt等のメタル3を付着する(図A)
。次に、フォトリソグラフィ技術1:よりフォトレジス
ト2のパターンを形成する(図B)。次に、At等のメ
タル3の露出部を化学エッチ(リン酸等によるクエット
エッチ又はCCt。
■Chemical etching method As shown in Figure 2, first, a metal 3 such as At is deposited on the entire surface of the silicon substrate 1 (Figure A) by vacuum evaporation.
. Next, a pattern of photoresist 2 is formed using photolithography technique 1 (Figure B). Next, the exposed portion of the metal 3 such as At is chemically etched (Quette etch or CCt using phosphoric acid, etc.).

ガス等によるドライエッチ)(二より除去する(図C)
o最後(=、フォトレジスト2を除去し、At等のメタ
ル3の所望のパターンを得る(図D)。
Dry etching with gas etc.) (Remove from the second step (Figure C)
o Finally (=, remove the photoresist 2 and obtain the desired pattern of the metal 3 such as At (Figure D).

ところが、第5図に示すように、エツチング時間を長く
しすぎると、フォトレジスト2直下のAt等のメタル5
もサイドエッチされる。したがって、化学エッチ法では
、エツチングの制御が難しく、エツチングしすぎるとA
I等の線幅が細くなり、所望の幅を得られないばかりか
、ひどい場合は、At等のメタルが断線する。
However, as shown in FIG. 5, if the etching time is too long, the metal 5 such as At directly under the photoresist 2
Also, the side is fucked. Therefore, with chemical etching methods, it is difficult to control etching, and excessive etching can lead to A.
The line width of I, etc. becomes thinner, and not only is it impossible to obtain the desired width, but in severe cases, the metal, such as At, becomes disconnected.

〔発明が解決しようとする問題点」 本発明は上述のリフトオフ法及び化学エッチ法における
欠点を解消し、At等のメタルの微細加工を可能にしよ
うとするものである。
[Problems to be Solved by the Invention] The present invention aims to eliminate the drawbacks of the above-mentioned lift-off method and chemical etching method, and to enable fine processing of metals such as At.

〔問題点を解決するための手段〕[Means for solving problems]

本発明においては、シリコン等の集積回路の製造工程に
おいて、次の■〜のの工程を有する。
In the present invention, the manufacturing process of an integrated circuit made of silicon or the like includes the following steps 1 to 2.

■ シリコン基数上に、フォトリソグラフィ技術により
、第1のフォトレジストのパターンを形成する。
(2) A first photoresist pattern is formed on the silicon substrate by photolithography.

■ その上に、真空蒸着法等により、全面にAt等のメ
タルを付着する。
(2) On top of that, a metal such as At is deposited on the entire surface by vacuum evaporation method or the like.

@サラL:その上l二、スピンオフ法等により、表面が
ほぼ平坦になるように第2のフォトレジスト膜を塗布す
る。
@Sarah L: Furthermore, a second photoresist film is applied using a spin-off method or the like so that the surface is almost flat.

■ このフォトレジスト膜をAt等のメタルの表面が露
出するまでエツチングする。
(2) This photoresist film is etched until the surface of the metal such as At is exposed.

■ ■で露出したAt等のメタルをリン酸等で工  1
ツテングする。
■ Process the metals such as At exposed in ■ with phosphoric acid etc. 1
Tsutengu.

の 最後にフォトレジスト膜を全て除去し、所望のA1
等のメタルのパターンを得る。
Finally, all the photoresist film is removed and the desired A1
etc. to obtain metal patterns.

〔作用〕[Effect]

本発明では、フォトレジスト上のAt等のメタルを先ず
完全に除去し、その後、露出しているフォトレジストが
除去されるから、フォトレジスト及びフォトレジスト上
(:付着していたA1等のメタルが残存する可能性は殆
んどなくなる。
In the present invention, the metal such as At on the photoresist is first completely removed, and then the exposed photoresist is removed. There is almost no chance of it remaining.

また、シリコン基板上に残存させるべきAt等のメタル
は、上部2両サイド共Cニフォトレジストで囲まれてい
るため、アルミ等のメタルのエッチャントと接触するこ
とがない。したがって、化学エッチ法で問題となる過剰
エツチングの現象が起こり得ない。
Furthermore, since the metal such as At which should remain on the silicon substrate is surrounded by the carbon photoresist on both upper sides, it does not come into contact with the etchant for the metal such as aluminum. Therefore, the phenomenon of excessive etching, which is a problem in chemical etching methods, cannot occur.

〔実施例〕〔Example〕

第1図1=おいて、図Aでシリコン基板1上にフォトリ
ソグラフィ技術により、フォトレジスト2のパターンを
形成し、図Bにおいて、真空蒸着法等により全面にA1
3を付着する。つづいて、図Cにおいて、スピンオン法
等によってフォトレジスト膜4を塗布する。このときフ
ォトレジスト膜4の表面は平坦になっていることが望ま
しい。次に、図D(二おいて、CF、ガスを用いたドラ
イ・エツチング法等によってフォトンシスト4を、A1
5の表面が露出するまでエツチングする。次に、図Eに
3いて、露出したA15 ’2 !jン酸酸等開用てエ
ツチングする。そして最後に図Fに示すよう(二、フォ
トレジスト2,4を全てレジストはくり液等(二より除
去する。
In Figure 1, a pattern of photoresist 2 is formed on the silicon substrate 1 in Figure A by photolithography, and in Figure B, a pattern of A1 is formed on the entire surface by vacuum evaporation.
Attach 3. Subsequently, in FIG. C, a photoresist film 4 is applied by a spin-on method or the like. At this time, it is desirable that the surface of the photoresist film 4 be flat. Next, photon cysts 4 are etched in A1 by a dry etching method using CF, gas, etc. in Figure D (2).
Etch until surface 5 is exposed. Next, there is 3 in figure E and exposed A15 '2! Etch using phosphoric acid, etc. Finally, as shown in FIG.

以上、All二ついて実施例開示したが、本発明はシリ
コン集積回路等の千六を体装置に用いる他の種々のメタ
ル、例えばMo 、 W 、 Ata等に広く適用でき
る。
Although the embodiments have been disclosed above using two alloys, the present invention can be widely applied to various other metals used in semiconductor devices such as silicon integrated circuits, such as Mo, W, Ata, etc.

〔発明の効果〕〔Effect of the invention〕

本発明(二よれば、上述のようにフォトレジスト上のA
1等のメタル3先ず完全に除去しく第1図り、E)、そ
の後、露出しているフォトレジストを除去するため、フ
ォトレジスト及びフォトレジスト上に付着していたAt
等のメタルが残存することがないので、At等のメタル
間のショートの恐れがなくなる。また、残存させるべき
At等のメタルは上部9両サイド共(ニフオトレジスト
で囲まれ保護され、At等のエッチャントと接触するこ
とがなく、化学エソy′″法で問題となる過剰エツチン
グの現象が生じない。したがって、化学エッチ法の欠点
であるAt等のメタルの線幅が細くなったり、最悪のケ
ースで断線するというようなことは起こらない。以上の
結果、本発明(二よればシリコン集積回路等の千4体装
置の製造に益するところ大である。
According to the present invention (2), A on photoresist as described above
1st grade metal 3 First, remove the photoresist and the At attached on the photoresist in order to remove the exposed photoresist.
Since metals such as At do not remain, there is no risk of short circuit between metals such as At. In addition, metals such as At that should be left on both sides of the upper part (surrounded and protected by niphoresist, do not come into contact with etchants such as At, and avoid the excessive etching phenomenon that is a problem with the chemical etching method). Therefore, the drawbacks of chemical etching methods, such as narrowing the line width of metal such as At or breaking the wire in the worst case, do not occur.As a result of the above, the present invention (according to This will greatly benefit the manufacture of 1,400-unit devices such as integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A−Fは本発明の一実施例の工゛程図、第21V
A−Dは従来の化学エッチ法の工程図、第5図A−Cは
従来のリットオフ法の工程図、第4図及び第5図は、そ
れぞれ従来のリフトオフ法及び化学エツy−法の欠点な
示す説明図。 1・・・シリコン基板
Figures 1A-F are process diagrams of an embodiment of the present invention, Figure 21V
A-D is a process diagram of the conventional chemical etching method, FIG. 5 A-C is a process diagram of the conventional lit-off method, and FIGS. 4 and 5 are disadvantages of the conventional lift-off method and chemical etching method, respectively. This is an explanatory diagram. 1...Silicon substrate

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に第1のフォトレジストのパターンをフ
ォトリソグラフィ技術により形成する工程と、該フォト
レジストのパターンを含む半導体基板上の全面にメタル
層を形成する工程と、第2のフォトレジスト膜を上面に
塗布する工程と、該第2のフォトレジスト膜を前記メタ
ル層の表面が露出するまでエッチングする工程と、該露
出したメタル層をエッチングして除去する工程と、残存
する第1のフォトレジスト及び第2のフォトレジスト膜
を全て除去する工程とを順に備えることを特徴とする半
導体装置の製造方法。
A step of forming a first photoresist pattern on the semiconductor substrate by photolithography technology, a step of forming a metal layer on the entire surface of the semiconductor substrate including the photoresist pattern, and a step of forming a second photoresist film on the upper surface. a step of etching the second photoresist film until the surface of the metal layer is exposed; a step of etching and removing the exposed metal layer; A method for manufacturing a semiconductor device, comprising the steps of: removing all of the second photoresist film.
JP59202688A 1984-09-27 1984-09-27 Manufacture of semiconductor device Pending JPS6180824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59202688A JPS6180824A (en) 1984-09-27 1984-09-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59202688A JPS6180824A (en) 1984-09-27 1984-09-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6180824A true JPS6180824A (en) 1986-04-24

Family

ID=16461504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59202688A Pending JPS6180824A (en) 1984-09-27 1984-09-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6180824A (en)

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