JPS6180918A - Serial parallel converting circuit - Google Patents

Abstract

PURPOSE:To simplify the correction of spectrum distortion by providing a random selecting circuit on a parallel outputting circuit which has been brought to serial-parallel conversion, and holding a random property between parallel outputs. CONSTITUTION:With respect to a parallel output bit number (n) (n=4), a serial memory circuit 104 of 2<n>(2<4>) bits and a parallel memory circuit 105 of 2<4> bits are provided, and brought to serial-parallel conversion by a clock signal 2. Subsequently, parallel outputs 24-39 are executed at every 2<4> clock by a frequency dividing circuit 107. As for this parallel output, a selecting circuit 106 is operated by an output of a control signal generating circuit 108 controlled by an output of the frequency dividing circuit 107, and said parallel output is selected at random at every four bits and fetched by the selecting circuit 106. In this way, a random property is held between signal trains, it is unnecessary to perform a conventional scramble random technique, and the correction of spectrum distortion can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a digital
This invention relates to a serial-to-parallel conversion circuit of n-To-Zero (j+3').

(Prior Art) Fig. 3 is a block diagram showing an example of a serial-parallel conversion circuit according to the prior art, and shows a case where the number of parallels n is 4 (n = 4). In Fig. 3, 101 is 4-bit serial memory circuit, 102 is a 4-bit parallel memory circuit, 106
For example, it is a frequency divider circuit.

Figure 4 is filled in! FIG. 3 is an explanatory diagram showing a conversion state for facilitating nf. 3 and 4, one series of input signals obtained by sequentially multiplexing four columns of asynchronous signals (signal line 1
(above) are sequentially stored in the 4-bit serial memory circuit 101. On the other hand, the input clock signal (signal line 2) is divided into four by the frequency dividing circuit 1.
The contents of the 4-bit memory circuit 101 are read out at once by the ratio output signal (signal line 6) obtained by dividing the frequency by 4 by 03, and are converted in parallel into 4 series signals (signals; i4 to i7).

The signals converted into parallel into four columns (signal lines 4 to 7) are nothing but signal columns formed from four columns of asynchronous signals before multiplexing as shown in FIG. 4. Here, @ t , b
r, cr, d ((1=1 p 2 e 3
t 4 ) indicates the signal of each column.

At this time, among the four asynchronous signals, only one series of signals is an information signal with randomness, and the other three series of signals have no signal and all bits are "1" or all bits are "0")
In this case, even among the four series of parallel signals that have been serial-parallel converted, only one series becomes a signal having randomness, and the other three series No. 13 have no signal. Since there is no randomness between the four series of signals mentioned above, the spectrum of the modulated signal will be subject to large distortions when multilevel modulation is performed. It will be included. For this purpose, a pattern rich in randomness with a long scramble pattern length is required for the conventional parallel signal. This method was used to create a scramble and provide randomness between the four signals to correct spectrum distortion.

(Problems to be Solved by the Invention) An object of the present invention is to provide n-column asynchronous signals (or synchronous signals)
The above drawbacks are removed by performing multilevel modulation when converting one series of 1h signals multiplexed from the columns into a multilevel signal,
It is an object of the present invention to provide a TI series-to-parallel conversion circuit configured to maintain randomness between signal streams regardless of the signal states of n series of asynchronous signals.

(Means for Solving the Problems) A serial-to-parallel converter according to the present invention includes: a 2n-bit serial memory circuit, a 2n-frequency divider circuit, a 2n-bit serial memory circuit, a control signal generation circuit, and a 2-selection circuit. It is composed of

The 2''' bit serial memory circuit temporarily stores the serial signal.

It is for remembering.

The 2n frequency divider circuit is for dividing the frequency of the clock signal of the serial signal.

The 2n-bit parallel memory circuit is for processing the contents of the 2n-bit serial memory circuit in parallel.

The control signal generation circuit is for generating a control signal from the output signal of the 2n frequency dividing circuit.

The selection circuit is for randomly controlling and selecting the output signals of the 2n-bit serial memory circuit into n columns based on the control signal. ! (Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the serial-parallel conversion circuit according to the present invention. This block diagram shows a case where the number of parallel connections n is 4 (n=4). In FIG. 1, 104 is a 24-pin serial memory circuit, 1o5 is a 24-bit parallel memory circuit, 1o6 is a selection circuit, 107 is a 24-frequency divider circuit, and 108 is a control signal generation circuit. Figure 2 makes it easier to understand.
FIG. 3 is an explanatory diagram showing the conversion state of the eye.

Input signal obtained by sequentially multiplexing four columns of asynchronous signals (
The signal 1) is sequentially connected to the 16-bit serial memory circuit 104.
is memorized. On the other hand, an output signal (signal line 21) obtained by dividing the human clock signal (signal line 2) by 16 by the 16 frequency divider circuit 107 causes the 16-bit serial memory circuit 10
The contents of 4 are read out at once and 16 series of signals (signal line 2
4 to 69). 16 frequency divided signal (signal @2
1) is set as one cycle, and the clock signal (signal line 2) is set to a high level for 4 cycles and a low level for 12 cycles, and is output from a divide-by-24 circuit. The reverse control signal generation circuit 108 generates the signal (signal line 22). Signal converted in parallel to 16 series signals (signal line 2
4 to 39) are distributed by the selection circuit 106 based on the head selection control signal (signal line 26), for example, so that four series of parallel signals (signal lines 40 to 43) are obtained in the arrangement shown in FIG. converted. In the converted signal sequence, the signal contents of the four asynchronous signals are dispersed, and if only the l sequence signal is an information signal with randomness, there will be randomness to the extent that it is between the signals converted into four sequences in parallel. sexuality will be preserved. When multilevel modulation is performed using these four series of signals, no large distortion occurs in the modulated signal spectrum. Incidentally, it is no secret that p1 can be arbitrarily distributed by changing the distribution method of the 16 series signals in the selection circuit 106.

(Effects of the Invention) As explained above, according to the present invention, by performing random distribution using only information signals without applying randomization techniques such as scrambling to serial-parallel conversion, randomness between parallel signals can be reduced. This has the effect of making it possible to maintain

The serial-to-parallel conversion technique (1) according to the present invention can be simply and easily achieved by using the random access memory that is currently available for general purpose, and random distribution can be easily performed. Furthermore, when the number of multiplexing stages and the number of serial-to-parallel conversions are different, the conventional circuit is sufficiently practical, but it is particularly effective when the two are the same.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial-to-parallel conversion circuit according to the present invention. FIG. 2 is an explanatory diagram of conversion states to facilitate understanding of the operation of the serial-to-parallel conversion circuit according to the present invention. FIG. 3 is a block diagram illustrating a series-to-parallel conversion circuit according to the prior art. The fourth octopus is an explanatory diagram of a conversion state to facilitate understanding of the operation of a serial-to-parallel conversion circuit according to the prior art. 101...4-bit serial memory circuit 102Fist...4-bit dish row memory circuit 1r33...Tatami 4 frequency division circuit 104...24-bit serial memory circuit 105...2
6-bit parallel memory circuit 106 - selection circuit 107 function 11@2 frequency divider circuit

Claims (1)

[Claims] A 2^n bit serial memory circuit for temporarily storing a serial signal, a 2^n frequency dividing circuit for frequency dividing a clock signal of the serial signal, and the contents of the 2^n bit serial memory circuit. A 2^n-bit parallel memory circuit for parallel processing, a control signal generation circuit for generating a control signal from the output signal of the 2^n frequency dividing circuit, and an output signal of the 2^n-bit parallel memory circuit. and a selection circuit for randomly controlling and selecting n columns under the control signal.