JPS6182465A - Dynamic memory cell - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to manufacturing semiconductor devices.

More particularly, the present invention relates to a dynamic read/write memory cell in a MOS VT, +S configuration.

[Conventional technology and its problems]

White, McA4ams and RMwine U.S. Pat. No. 4,081,701 (i6k RAM
), or Mem 16) xancLer, Whit
U.S. Patent No. 4.295.995 named e and Rao (
Semiconductor dynamic RAM devices of the type disclosed in U.S. Pat.
．． No. 121. Both patents are assigned to Texas Instruments. For example, 1st message beeps) DR
Various methods have been proposed to reduce the size of the capacitor in order to reduce the size of dynamic RAM cells to the extent necessary to fabricate extremely high density RAMs, such as AM. The size of the capacitor is
In order to store a sufficient amount of electricity, it cannot be made smaller than a certain size. One method of reducing the area of a capacitor while still maintaining a sufficient amount of stored electricity is described in U.S. Pat. No. 4,240,092, filed under Rao and assigned to Texas Instruments. As disclosed, the oxide thickness is reduced.

In this method, yield and reliability considerations limit the oxide thickness to a range of approximately 100 to 200 mm. Another way to increase the capacitance per unit area is to increase the plate area by etching depressions or grooves in the area of the capacitor. An example of this method is disclosed in Texas Instruments Co. K. also assigned US Pat. No. 4,225,945.

[Problem that the invention seeks to solve]

The main object of the present invention is to provide a highly integrated dynamic RAM.
It is about an improved process for manufacturing cells. More specifically, it involves an improved process that increases the plate area for capacitance by etching grooves into the storage capacitor area. Another object of the present invention is to provide an improved method of fabricating a dynamic RAM cell having a trench capacitor without corroding the lower portion of the protective film during the trench etching process. Yet another object of the invention is to provide a simple and reliable process for manufacturing channel capacitors.

[Means for solving problems]

According to one embodiment of the present invention, a dynamic one transistor read/write memory cell uses a trench capacitor to increase the amount of electricity stored. A trench is etched into the silicon surface at the same N+ capacitor area as the diffused N+ bit line, and then a thick oxide is grown over this bit line and over the capacitor area. let However, thick oxide is not grown inside the trench. Oxide is regrown on the partially etched portions under this thick oxide in the trench, followed by etching to bring the trench to its final depth. This reduces the effect of corrosion on the lower part of the protective film. The upper plate of the capacitor is a polysilicon layer extending into the trench, also creating field plate isolation on the surface of the silicon bar. A passive metal word line forms the r-t of the access transistor at the hole in the polysilicon field plate.

〔Example〕

The novel features of the invention are pointed out in the claims. The invention itself, as well as other features and advantages, will be best understood from the accompanying drawings and the detailed description below.

A one-transistor dynamic memory cell fabricated in accordance with the present invention is illustrated in the drawings of FIGS. 1-5. This cell has an N-channel access transistor 10 and a storage capacitor 11 fabricated in a silicon substrate 12. Transistor 10 has a metal gate 13. This gate is a part of the IJ tube 14 (elongated strip), and this strip is a part of the memory
It constitutes the gonadal tract (i.e., word tract) of the array. The transistor's input 15 is part of an elongated bit line 16 perpendicular to the word line 14.

The illustrated board portion has a size of approximately 3.8+zX10x+
z (150 mils x 400 mils) f1') is a tiny piece of silicone bar. This silicon bar was transferred to Texas Instruments,
220 of these cells, or 1,048
．． It has 576 pieces.

The bit line 16 is buried under a thick thermal oxide layer 17. Therefore, the metal word line can pass directly over this bit line.

Lateral isolation in the field plate 18
obtained by. This field plate is constructed of polysilicon in this embodiment and is electrically connected to the substrate voltage Vsa. field plate 18
Hole 19 within defines the area of gate 13 of transistor 10 .

According to the invention, the capacitor 11 has a groove 20. This 420 is F[K (Reactive construction on Etc.
A hole etched into silicon by a fully anisotropic etching technique (such as reactive ion etching). Groove 20 has a width of approximately 1 micron and a depth of approximately 6 microns. A thin silicon bolide layer 21 is the dielectric of this capacitor. Thin silicon oxide 22 is the insulator for the gate of the transistor. Thicker oxide coating layer 2
3 and silicon nitride layer 24 provide an insulator under field plate 18. A grounded field P plate 18 insulates the polysilicon 16 from the metal word line and is also flat to the metal line 14.

Provides a smooth surface. - the trench 20 and the capacitor 11 are sunk into a square area of the field oxide 28; , field oxide 28 has a door region 29 below it. This is similar to the case with oxide 17 and bit line 16. This N+ region 29 serves as the source of access transistor 10 and is separated from drain 15 by the channel length of this transistor.

The method of manufacturing the cell shown in the drawings of FIGS. 1-5 will be explained in the drawings of FIGS. 6-9. A thin plate of silicon has a 230 layer of thermal silicon oxide approximately 100 OA thick grown on its surface. A layer 24 of silicon nitride is then placed on top of this oxide.
is deposited.

This oxide-nitride sandwich structure is patterned by a photolithographic step to create exposed areas 30 for the bit lines 16 and areas 31 in which the capacitors are to be fabricated. By ion implantation,
N+ regions 32 and 33 are created. These will later create the C bit line 16 and the N+ region 29.

As shown in FIG. 7, an etch mask 34 is deposited to create the grooves. This etching mask has a thickness of approximately 80mm. silicon oxide to [ ], the silicon oxide being produced by low pressure chemical vapor deposition. Photoresist can also be used if the selective etching of silicon to photoresist is sufficiently high. To define grooves 20, holes 35 are made in layer 34 by photolithography. Using an anisotropic etch such as R-E, trenches 20 are dug into the capacitor area to a depth of about 6 microns. In fact, depending on the etching process used,
The bottom of the groove is not the same width as the top, the bottom is a little narrower. Therefore, this groove is not completely rectangular but somewhat conical.

In the present invention, this groove etching is a two-step process. The first etch is shallow, as shown in the enlarged view of FIG. 7a. This etching removes the silicon in the hole, but also removes the silicon in the area 33 under the mask 34.
The etching is also etched to remove some of the area 36 surrounding the hole.

Next, thermal oxidation is performed in steam to grow oxide 36a in region 36. As shown in Figure 7b, an oxide 3T is also grown in this trench, but this is very thin due to the amount of silicon doping. This oxide in the shallow trenches is removed by deep etching.

The oxide 36& in the region 36 acts as an etch-preventing material to prevent the lower part of the mask 34 from being etched any further, thereby allowing the etching process to dig the trench to a predetermined depth. Figures 1 and 2
In the completed structure, such as ring 36' of FIG. 4, the extent to which region 36 extends is very small.

This trench mask 34 is removed using a conventional oxide etch such as Hl.

Etching with this etchant will stop at nitride 24. As shown in Figure 8,
Monooxides 1T and 28 are then grown over r regions 32 and 33. This oxide grows many times faster on the H+ silicon than on the very slightly V-pushed silicon in trench 20. Thus, oxides 17 and 28 are approximately 4000 µm thick, but only approximately 200 µm thick within the trench. This thin oxide is grown into the trench and removed. It is then regrown as oxide 21. As shown in FIG. This layer of polysilicon thus covers the sidewalls of the trench and the surface of the lamella with approximately the same thickness of about 250 OA.
An oxide layer 26 is deposited over the entire surface of the sheet, planarizing the surface and filling the grooves 20. This oxide 26 will also isolate the word line from the surface. This polysilicon/oxide stack is patterned using photoresist, and Field 1? ! rate 18 and capacitor plate 25 are created. That is, a hole 19 is drilled for the transistor 10.

Returning to the drawings of FIGS. 1-4, the oxide in the gate region is removed and oxide 22 is re-grown by growth. At this point, thermal oxide is grown on the exposed edges of the polysilicon near the periphery of hole 190. Then, a word track is created. The word line is created by depositing a layer of molybdenum over the entire surface of the sheet and patterning it by photolithography.
In this case, a gate 13 and a word line 14 are created.

A protective overcoat layer (not shown) is created on the top surface, and the overlayer is then patterned to expose the bonding para-V. This sheet is then inspected and cut into individual bars. These bars are mounted inside a semiconductor package.

Although the invention has been described based on illustrative embodiments, this description is not meant to be limited thereto. Based on this specification, it will be apparent to those skilled in the art that various modifications to the illustrative embodiments and other embodiments are possible. It is therefore intended that such modifications and other embodiments be within the scope of the following claims.

〔Effect of the invention〕

According to the present invention, a capacitor that occupies an extremely small area on a semiconductor substrate but has a sufficiently large capacitance can be manufactured with high yield and high reliability. This allows very small dynamic memory cells to be placed on the substrate, and therefore very large densities.

[Brief explanation of the drawing]

FIG. 1 shows a memory cell in a semiconductor dynamic read/write memory having a memory cell according to the invention.
FIG. 2 is a cross-sectional view of the cell of FIG. 1 taken along line 2--2 of FIG. 1; FIG. 6 is a cross-sectional view of the cell of FIG. 1 taken along line 6 of FIG. 4 is a cross-sectional view of the cell of FIG. 1 taken along line 4--6 of FIG. 1; FIG. 5 is a cross-sectional view of the cell of FIG. 1 to 4 are schematic electrical circuit diagrams of the memory cells of the drawings in FIGS. 1 to 4, and the drawings in FIGS. Cross-sectional view of the cell in Figure. [Description of symbols] 10 Access transistor 11 Capacitor 13 Metal gate 14 Word line 16 Bit line IT, 2B Thick thermal oxide 18 Field plate 20 groove 29 11+ region

Claims (21)

[Claims] (1) A dynamic memory cell fabricated in one surface of a semiconductor substrate, having a source-drain path at the channel region, and having a source-drain path above the channel region and thin from the channel region. an access transistor having a metal gate separated by a gate oxide; a metal word line that is perpendicular to the bit line on the surface and has the metal gate as a part thereof; and the N^+ region of the bit line is above the bit line. separated from the word line by a thick thermal field oxide; a trench in the surface etched into the interior of the surface; a capacitor region having a thick thermal field oxide overlying the N^+ region and surrounding the trench and surrounding the trench.
a region of thermal field oxide inserted into the ^+ region, covering the surface over the capacitor region, the bit line, and all regions other than the channel region of the transistor; , a field plate having a conductive layer extending into the trench and insulated from silicon by a thin oxide in the trench to become an upper plate of the capacitor. (2) The memory cell of claim 1, wherein the field plate is isolated from the surface by an oxide layer and a nitride layer in a region excluding the capacitor region and the bit line. . (3) In claim 1, the capacitor region is laterally separated from the drain region by the channel region along the surface, and the N^+ region within the capacitor region is separated from the drain region by the channel region. a memory cell forming a source of said transistor. 4. The memory cell of claim 1, wherein the thickness of the field oxide above the bit line is approximately the same as the thickness of the field oxide in the capacitor region. 5. The memory cell of claim 1, wherein a dielectric coating on said field plate fills said groove to provide a high profile surface for said metal word line. . 6. The memory cell of claim 1, wherein the trench width is no greater than about 1 micron and the trench depth is at least about twice the width. 7. The memory cell of claim 1, wherein the substrate is P-type silicon, the metal word line is molybdenum, and the conductive layer is polysilicon. (8) A method of fabricating a memory cell on one surface of a semiconductor substrate, the method comprising: forming a patterned oxide mask on the surface to expose bit line regions and capacitor regions; , implanting an impurity into the surface in the bit line region and the capacitor region, thereby resulting in a heavily doped region, and the oxide mask implanting an impurity into the surface; said step of implantation being interrupted by a mask portion; and step of masking said surface to expose only a portion of said capacitor area of said surface; and creating a groove having a depth with a dimension greater than its width dimension. a first step of etching the surface within the portion, etching to a depth just below the heavily doped region;
an etching step, followed by a step of growing a thermal oxide inserted into the heavily doped region and surrounding the trench, and then further performed to bring the trench to the finished depth. a second etching step to etch remaining portions; and a step of growing a thermal oxide to form a thick thermal oxide on the surface in the bit line region and in the capacitor region. growing a target oxide, wherein the impurity creates a heavily doped region below the thermal oxide, and the thickness of the thermal oxide in the trench is greater than the thickness of the thermal oxide above the heavily doped region. said step of growing a thermal oxide of smaller and smaller thickness; and a conductive layer extending within said trench and insulated from said substrate by an insulating sheath. forming a hole in the conductive layer in a channel region between the bit line and the capacitor region; depositing a conductor on the surface and patterning the conductor. forming a transistor gate in the hole and in the word line in the surface and perpendicular to the bit line. (9) In claim 8, the substrate is silicon, the conductive layer is polycrystalline silicon, the conductor is molybdenum, and the impurity is N-type. A manufacturing method characterized by. (10) In claim 8, the oxide mask is silicon nitride, and the surface under the conductive layer other than the bit line region, the capacitor region, and the channel region is A manufacturing method in which the silicon nitride is created in a predetermined location. (11) The method of claim 8, wherein after the step of growing a thermal oxide, the oxide mask is removed only from the channel region, and the oxide mask is placed under the conductive layer. is a manufacturing method that has a step in which it is left in place. (12) The manufacturing method according to claim 8, further comprising the step of filling the groove with an insulating material after the step of forming the conductive layer. (13) In claim 8, the substrate is P
the conductor is metal, and the impurity is N-type, and after the step of thermally growing an oxide, the oxide mask is applied to the channel. A manufacturing method that includes the step of removing only from the area. (14) In claim 13, the oxide mask is silicon nitride, and a predetermined area in the surface under the conductive layer other than the bit line region, the capacitor region, and the channel region A manufacturing method in which the silicon nitride is left at the position. (15) A method of fabricating a memory cell on one surface of a semiconductor substrate, the method comprising: forming a patterned oxide mask on the surface to expose bit line regions and capacitor regions; , implanting an impurity into the surface in the bit line region and the capacitor region, thereby resulting in a heavily doped region, and the oxide mask implanting an impurity into the surface; said implantation step being obstructed by a mask portion; said surface should be masked to expose only a portion of said capacitor area of said surface, and a trench should be made with a depth having a dimension larger than its width dimension; etching the surface in the portion; and growing the oxide, growing a thick thermal oxide on the surface in the bit line region and in the capacitor region; The impurity creates a heavily doped region below the thermal oxide, and the trench has a thermal oxide layer of a thickness that is less than the thickness of the thermal oxide above the heavily doped region. said step of growing a thermal oxide to grow an oxide; creating a conductive layer on said surface extending into said trench and insulated from said substrate by a cover of insulator; drilling a hole in the conductive layer in a channel region between a bit line and the capacitor region; depositing a conductor on the surface and patterning the conductor so as to form a conductor in the surface; forming a transistor gate in a word line perpendicular to the bit line and in the hole. (16) In claim 15, the substrate is silicon, the conductive layer is polycrystalline silicon, the conductor is molybdenum, and the impurity is N-type. A manufacturing method characterized by. (17) In claim 15, the oxide mask is silicon nitride, and the surface under the conductive layer other than the bit line region, the capacitor region, and the channel region is A manufacturing method in which the silicon nitride is created in a predetermined location. (18) The method of claim 15, wherein after the step of thermally growing oxide, the oxide mask is removed only from the channel region, and the oxide mask is placed under the conductive layer. A manufacturing method that has a step of leaving it behind. (19) The manufacturing method according to claim 15, further comprising the step of filling the groove with an insulating material after the step of forming the conductive layer. (20) Claim 15, characterized in that the substrate is P-type, the conductor is metal, and the impurity is N-type, and After said step of growing said oxide mask, said method comprises the step of removing said oxide mask only from said channel region. (21) In claim 20, the oxide mask is silicon nitride, and a predetermined area in the surface under the conductive layer other than the bit line region, the capacitor region, and the channel region A manufacturing method in which the silicon nitride is left at the position.