JPS6182476A - Semiconductor device - Google Patents

Abstract

PURPOSE:To set to the necessary minimum limit withstand voltage and to prevent a damage from occurring due to the concentration of a breakdown current by providing a region made of a high density impurity by the first conductive type substrate to contact directly with the second conductive type high density impurity region. CONSTITUTION:A P<+> type field inversion preventive layer 22, a field oxide film 23, a gate oxide film 24 and a gate oxide 25 are formed on the surface of a P type silicon substrate 21. Boron ions are implanted to form P<+> type impurity regions 29, 30 arsenic ions are implanted to form N<+> type impurity regions 31, 32 phosphorus ions are implanted to form N<-> type impurity regions 33, 34 to form a source region 35 and a drain region 36. The regions 29, 30 are disposed to contact directly under the regions 31, 33. An interlayer insulating film 37 is formed, and an N-channel field effect transistor is formed by forming an aluminum electrode 39. Thus, the withstand voltage of the N<+>-P<-> junction is determined by the density of the P<+> region 30, and the withstand voltage can be controlled to the prescribed value by the forming conditions of the region 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a field effect transistor that requires high voltage operation.

(Technical background of the invention and its problems) As is well known, Ll is becoming increasingly finer due to demands for cost reduction and performance improvement, and as a result, the gate film thickness is reduced to nil, and the effective increase in substrate concentration,
The drain breakdown voltage is decreasing due to reduction in junction width and height. On the other hand, ICs for controlling EPROMs, 1, and decitrons that require high-voltage operation, such as i, t,
It is necessary to set the drain voltage to a relatively high breakdown voltage. As a transistor structure that satisfies these requirements, a low concentration impurity region is provided around the source and drain regions, and the source and drain liIM! Conventionally, a structure has been used that weakens the electric field applied to the bond between the substrate and the substrate.

This transistor will be explained with reference to FIG.

1 in the diagram. is a semiconductor substrate having a field region 2 on its surface. N-type source and drain regions 3.4 are provided in the element region defined by the field region 1g2&:II. The source 3 is composed of an N4'' type impurity region 7a and a surrounding N- type impurity region 6a.Similarly, the drain region 4 is composed of an N+ type impurity region 5b and an N+ type impurity region 5b. A gate electrode 8 is provided on the gate region between the source and drain regions 3.4 with a gate insulator 117 interposed therebetween. An interlayer insulating film 9 is provided, and a contact hole 10 is provided in the interlayer insulating film 9 corresponding to the impurity region 5a of the drain region 4. An AQ electrode 11 is provided in this contact hole 10. , 12 in the figure is a field inversion prevention layer.

Here, the breakdown path of the field effect transistor shown in FIG. 1 will be explained. ■ to ■ in the figure indicate possible breakdown paths, which are described below. ■: This is breakdown of the N- type impurity region 6b that constitutes a part of the drain region 4, and in addition to the concentration of the impurity region 6b, the substrate 1, and the curvature of the impurity region 6b, the thickness of the gate insulator 117 and the gate potential to be influenced. (2) Breakdown of the impurity region 6b in areas other than the negative 8 portion is affected by the concentration and curvature of the impurity region 6b, as well as the concentration when it contacts the field inversion prevention layer.

■: N+ type impurity 'fIlI slope near the boundary between the R region 5b and the N- type impurity region 6b, which is affected by the concentration of the substrate 1, the curvature of the impurity region 5b, and the impurity region 6b. . ■: Impurity! Due to the breakdown between the i region 5b and the substrate 1, the substrate 1
It is determined by the degree of S. (2): This is a bunch-through phenomenon between three or four gates of the source and drain gates of the transistor, and in general, in the case of a high voltage transistor, the gate length is set so that this phenomenon does not occur. In this surrender, ■
The breakdown at , @ is approximately determined by the substrate concentration and the curvature of the impurity region 5b (determined by the depths of the impurity regions 5b and 6b, etc.) since the concentration of the N4 type impurity region 5b is usually sufficient. The substrate concentration and the depth σ of the impurity region 5b are limited by other factors such as transistor characteristics (back gate effect, mobility, etc.), resistance of the impurity region 5b, reliability issues in the contact hole 10, etc., and are generally not within the target range. It is sufficiently higher than the operating voltage. On the other hand, the breakdown at ■ and ■ can be changed by appropriately setting the concentration of impurity region 6b. For example, the lower the concentration of impurity region 6b, the weaker the electric field between impurity region 6b and substrate 1.
Pressure resistance improves. However, lowering the concentration of impurity region 6b increases the parasitic resistance of impurity region 6b, reducing the driving power of the transistor. Therefore, it is desirable to set the withstand voltage to a level that satisfies the operating voltage specifications of the transistor to minimize the reduction in drive capability. Therefore, the breakdown voltage of the above transistor is usually determined by the breakdown voltage of (1) or (2). In this case, the breakdown current when an excessive voltage is applied to the drain region 4 is
@Pass through the joints of the scooping areas 5b, 6b and ■, ■, and the substrate 1
Exit to. However, if N flow flows along the above path,
Parasitic resistance in the impurity region 6b and current concentration at the edge of the contact hole tend to cause local heat generation, which often leads to breakdown of the junction, penetration of the A.degree. C. electrode 11 into the substrate 1, and permanent destruction. Of course, in general, transistors operate at voltages that do not cause breakdown, but transient overvoltage due to static electricity or noise during operation is a phenomenon that is often experienced, and as a result, the reliability of the transistors described above is extremely low. It has become something that lacks. The above-mentioned destruction phenomenon appears more prominently as the withstand voltage becomes higher and as the depth of the impurity region becomes shallower.

Here, in order to avoid heat generation due to the concentration of current mentioned above,
By setting the breakdown voltages of ■ and ■ lower than those of
It is sufficient if it passes through the joints b, ① and ② and exits to the substrate 1. To achieve this, lower the concentration of the impurity region 6b,
(2) Increase the withstand voltage or conversely increase the substrate concentration or impurity layer 1m! ■, ■ by reducing the depth of impurity region 5b while keeping the depth ratio of 5b and 6b above a certain level.
A method is needed to lower the withstand voltage. However, in the former case, the breakdown voltage is increased more than necessary, which increases the parasitic resistance of the impurity layer region 6b, which is not preferable. On the other hand, in the latter case, increasing the substrate concentration adversely affects the operating characteristics of the transistor, such as increasing the back gate effect. Further, there are reliability and technical limits to reducing the depth of impurity regions 5b and 6b.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to set the necessary minimum breakdown voltage regardless of the substrate concentration or the depth of the impurity region, suppress the increase in parasitic resistance, and reduce the concentration of breakdown current. An object of the present invention is to provide a semiconductor device that can prevent destruction.

[Summary of the invention]

The first invention of the present application is directed to at least a first region (a part of the drain region) made of impurities of a high concentration of a second conductivity type, and an impurity of a first conductivity type of a higher concentration than the substrate so as to be in contact with the region. The main idea is that the above object is achieved by providing a third region consisting of:

The second invention of the present application is characterized in that a fourth region made of a high concentration impurity of a second conductivity type, which is spaced apart from at least a drain region and electrically connected to the same region, is provided with a first conductivity type impurity so as to be in contact with the fourth region. This is intended to provide the same effect as the first invention of the present application by providing a sixth region made of impurities at a higher concentration than the substrate.

[Embodiments of the invention]

The manufacturing process of an N-channel field effect transistor according to an embodiment of the present invention is shown in FIGS. 1(a) to 1(e) below.
This will be explained with reference to FIG.

(1) First, a P" type field inversion prevention layer 22 and field oxide 1123 were formed on the surface of a P type silicon substrate 21 with a concentration of about I x 101 S/an3 by a well-known method such as the Kobusina method. Continued Then, in the device region surrounded by the field oxide film 23, a thickness of ~700 mm is formed.
After forming the gate oxide 11124, a polycrystalline silicon layer is deposited and patterned to form the gate electrode 25.
was formed (as shown in FIG. 1(a)). Then, the first
After forming the resist layer 26, openings were formed in the resist layer 26 corresponding to part of the portions where the source and drain regions, which will be described later, are to be formed, by photolithographic etching (PEP). Furthermore, resist layer 2
6 as a mask, for example, boron is accelerated at a voltage of 140Ke.
1 (b) to form P+ type impurity layers 27 and 28).

(2) Next, after peeling off the first resist layer 26, heat treatment is performed at 1000° C. for 120 minutes in order to smooth the profile of the impurity layers 27 and 28 and stabilize the process. P+ type impurity layer vt as a region
<p+ region 29.30 was formed. Continuously, 1. A second resist layer (not shown) was formed in which portions corresponding to portions where the source and drain regions (to be described later) were to be formed were opened.

Thereafter, using this resist layer as a mask, arsenic, for example, is introduced into the substrate 21 by ion implantation or solid phase diffusion to form an N'' type impurity region (N
'''Region) 31.32 was formed.In addition, N+ area 31
．． The surface concentration of 32 is ~10/cIR3 after the final step,
The depth was about 0.4μ door.

After that, the second resist layer was peeled off (as shown in FIG. 1(C)). Furthermore, for example, phosphorus is ion-implanted into the substrate 21 under the conditions of an acceleration voltage of 100 KeV and a dose setting of 2×10 12 /ci, and an N- type inert material is formed as a second region around each of the N+ regions 31 and 32. Area (N-area) 33.34
was formed. Here, a source region 35 was formed from the N" region 31 and the surrounding N- region 33, and a drain region 36 was formed from the N+ region 32 and the surrounding N- region 34. Also, the P1 region 29. 30 is the N+ area 31
．． 33 so as to be in contact with these areas (as shown in FIG. 1(d) and FIG. 2).

Note that FIG. 1(d) is a sectional view taken along the line xx in FIG. 2. In addition, the N+ region 32 and the P1 region 3 in FIG. 1(d)
The impurity profile at 0 is as shown in FIG. Subsequently, after forming an interlayer insulating film 37 on the entire surface, an interlayer insulating film 37 corresponding to a part of the N"l region 31, 32 is formed.
I37 is opened, a contact hole 38.38 is formed, and an Aβ electrode 39 is further inserted into this contact hole 38.38.
．． 39 was formed to manufacture an N-channel field effect transistor (as shown in FIG. 1(e)).

In the field effect transistor according to the present invention, as shown in FIG.
．． It has a structure in which 30 are provided.

According to the present invention, by providing the P+ regions 29 and 30 at predetermined positions, the following effects can be achieved.

■, as seen in the impurity profile in Figure 4, P
The lI on the 9 side is ~2.2X 10" @/cm3, making it a one-sided poisoning junction, and the withstand voltage at this part is approximately ~3.5
It is about V. Also, since the withstand voltage of the N- region 34 to the substrate 21 is about 45V, the breakdown is ~35V and the N+
~P4'' junction. Therefore, compared to the conventional case, the current path does not pass through the N-region 34, which has a high resistance, and current concentration can be prevented, thereby preventing destruction due to local heat generation. Note that the arrows in FIG. 1(e) indicate current paths due to breakdown.

(2) Since the withstand voltage at the N+ to P- junction is determined by the concentration of the P4'' region 30, its controllability can be made very good by optimizing the conditions for forming the P+ region 30.

In the above embodiments, a case has been described in which both the source and drain regions are made to have a high breakdown voltage, but the invention is not limited to this, and only the drain side may be made to have a high breakdown voltage depending on the usage conditions of the transistor.

In the above embodiment, a case has been described in which the N- region is provided in both the source and drain regions, but the N- region is not limited to this, and may be provided only in the train a region side.

In the above embodiment, the P1 region was formed only in the flat portion of the N3 region in consideration of the stability of its effect.

It may be in contact with the boundary of the N"WA area and the N- area.

The semiconductor device according to the present invention is not limited to the one of the above-mentioned embodiments, but may be of the type shown in FIG. 5, for example, if there is room for the pattern. In the figure, reference numerals 1 and 41 indicate an N+ type impurity region as a fourth region. Around this region 41, an N- type impurity region 42 as a fifth region is provided.

Directly below the region 41, a P+ type impurity region 43 as a sixth region is provided so as to be in contact with the region 41. The N+ type impurity region bA41 is connected to the N'' region 3 through the A2 electrode 45 provided in the contact hole 44.
2 and is electrically connected.

In the above embodiment, the case of an N-channel field effect transistor has been described, but the present invention is not limited to this, and can be similarly applied to a P-channel field effect transistor or a complementary field effect transistor.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a highly reliable semiconductor device which has remarkable effects such as being able to control the withstand voltage to a predetermined value and being able to prevent destruction due to sinking current. be.

[Brief explanation of the drawing]

1(a) to 1(e) are cross-sectional views showing the N-channel field effect transistor according to the present invention in the order of manufacturing steps, FIG. 2 is a plan view of FIG. 1<1Ei), and FIG. 3 is a conventional FIG. 4 is a cross-sectional view of a field effect transistor, FIG. 4 is an impurity characteristic diagram of the impurity II region of the transistor according to the present invention, and FIG. 5 is a cross-sectional view of a field effect transistor according to another embodiment of the present invention. 21... P type silicon substrate, 23... Field inversion prevention layer, 24... Gate oxide film, 25... Gate electrode, 29.30.43...-P+ type impurity region (P
"region), 31.32.41...N+ type impurity region (N+ region, 33.34.42.-N" type impurity region (N- region), 35... source region, 36.・
・Drain region, 38... Funtakt hole, 39・
...AQN pole.

Claims (2)

[Claims] (1) A first conductivity type semiconductor substrate, a first region made of a second conductivity type high concentration impurity provided on the surface of this substrate, and a first region surrounding the first region and in contact with a gate region on the surface of the substrate. a second conductivity type drain region composed of a second region made of a second conductivity type low concentration impurity provided as in the above, and a gate electrode provided on the gate region via a gate insulating film; a third region made of impurities at a higher concentration than the substrate of the first conductivity type and provided directly under the first region and in contact with the region, the third region being formed by the first region and the third region; A semiconductor device characterized in that a breakdown voltage of a junction formed between the second region and the substrate is lower than a breakdown voltage of a junction formed between the second region and the substrate. (2) A first conductivity type semiconductor substrate, a first region made of a second conductivity type high concentration impurity provided on the surface of the substrate, and a first region surrounding the first region and in contact with the gate region. a second conductivity type drain region composed of a second region made of a second conductivity type low concentration impurity provided as in the above, and a gate electrode provided on the gate region via a gate insulating film; a fourth region made of a second conductivity type high concentration impurity provided on the surface of the substrate, spaced apart from the drain region and electrically connected to the same region;
a fifth region made of a second conductivity type low concentration impurity and provided to surround the fourth region;
a sixth region made of a higher concentration impurity than the substrate of the first conductivity type and provided directly under the region and in contact with the region, and a junction formed between the third region and the fifth region; A semiconductor device characterized in that a breakdown voltage of the second region is lower than a breakdown voltage of a junction formed between the second region and the substrate.