JPS6183340U - - Google Patents
Info
- Publication number
- JPS6183340U JPS6183340U JP16836284U JP16836284U JPS6183340U JP S6183340 U JPS6183340 U JP S6183340U JP 16836284 U JP16836284 U JP 16836284U JP 16836284 U JP16836284 U JP 16836284U JP S6183340 U JPS6183340 U JP S6183340U
- Authority
- JP
- Japan
- Prior art keywords
- level
- switch
- output terminal
- capacitor
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000007599 discharging Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図はそのタイムチヤート、第３図は本考案の他の
実施例を示す回路図、第４図はそのタイムチヤー
ト、第５図は本考案の応用例を示す回路図である
。
図中、ＳＷ１は手動式スイツチ、Ａ，Ｂは出力
端子、Ｃ１はコンデンサ、Ｒ３，Ｒ１１は充電用
抵抗、Ｒ５〜Ｒ７，Ｒ１３〜Ｒ１５は放電用抵抗
、Ｑ１〜Ｑ４，Ｑ１１〜Ｑ１３はトランジスタで
ある。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing another embodiment of the present invention, FIG. 4 is a time chart thereof, and FIG. 5 is a circuit diagram showing an application example of the present invention. In the figure, SW 1 is a manual switch, A and B are output terminals, C 1 is a capacitor, R 3 and R 11 are charging resistors, R 5 to R 7 , R 13 to R 15 are discharging resistors, and Q 1 ~ Q4 , Q11 ~ Q13 are transistors.
Claims (1)
、２つの独立した出力端子と、該スイツチがオン
になると充電されるコンデンサと、該コンデンサ
の充電用抵抗および放電用抵抗と、該スイツチが
オフの間は上記２つの出力端子を同じレベルに保
ち、また該スイツチがオンになると直ちに一方の
出力端子のレベルを反転させ、更にオン時間が継
続して前記コンデンサが所定の電圧まで充電され
ると他方の出力端子のレベルを反転させると共に
該一方の出力端子のレベルを再反転させるトラン
ジスタ回路とを備えてなることを特徴とするスイ
ツチング回路。 An input terminal to which one manual switch is connected, two independent output terminals, a capacitor that is charged when the switch is turned on, a charging resistor and a discharging resistor for the capacitor, and an input terminal when the switch is turned off. During this period, the two output terminals are kept at the same level, and as soon as the switch is turned on, the level of one output terminal is inverted, and when the on-time continues and the capacitor is charged to a predetermined voltage, the level of the other output terminal is maintained. 1. A switching circuit comprising a transistor circuit which inverts the level of an output terminal of the switching circuit and re-inverts the level of the one output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16836284U JPS6183340U (en) | 1984-11-06 | 1984-11-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16836284U JPS6183340U (en) | 1984-11-06 | 1984-11-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6183340U true JPS6183340U (en) | 1986-06-02 |
Family
ID=30726135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16836284U Pending JPS6183340U (en) | 1984-11-06 | 1984-11-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6183340U (en) |
-
1984
- 1984-11-06 JP JP16836284U patent/JPS6183340U/ja active Pending
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