JPS6183344U - - Google Patents
Info
- Publication number
- JPS6183344U JPS6183344U JP16665584U JP16665584U JPS6183344U JP S6183344 U JPS6183344 U JP S6183344U JP 16665584 U JP16665584 U JP 16665584U JP 16665584 U JP16665584 U JP 16665584U JP S6183344 U JPS6183344 U JP S6183344U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- clock pulse
- starts operating
- pulse input
- lower counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の実施例を示すブロツク図であ
り、第２図は第１図に示す実施例の各部の動作を
示すタイムチヤートであり、第３図は本考案の第
２の実施例を示すブロツク図である。第４図はカ
ウンタ回路の従来例を示すブロツク図であり、第
５図は第４図に示す従来例での各部の動作を示す
タイムチヤートである。
３…ＡＮＤ素子、４…抵抗、５…コンデンサ、
６，７…ＲＯＭ、８…コンパレータ、１１…下位
カウンタ、１２…上位カウンタ、２１…下位遅延
素子、２２…上位遅延素子。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of each part of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. FIG. 4 is a block diagram showing a conventional example of a counter circuit, and FIG. 5 is a time chart showing the operation of each part in the conventional example shown in FIG. 3...AND element, 4...Resistor, 5...Capacitor,
6, 7... ROM, 8... Comparator, 11... Lower counter, 12... Upper counter, 21... Lower delay element, 22... Upper delay element.
Claims (1)
クロツクパルスを与えるとき、下位のカウンタか
ら動作を開始して下位カウンタがカウントアウト
すれば順次上位のカウンタが動作し、またはその
逆の動作をするよう構成されているカウンタ回路
において、上記カウンタよりも下位カウンタに入
力するクロツクパルスの方が遅延するような遅延
手段を各カウンタのクロツクパルス入力部に備え
ることを特徴とするカウンタ回路。 When a common clock pulse is applied to multiple counters connected in series, the lower counter starts operating, and when the lower counter counts out, the upper counter starts operating, or vice versa. 1. A counter circuit characterized in that the clock pulse input section of each counter is provided with delay means for delaying the clock pulse input to the lower counter than the counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16665584U JPS6183344U (en) | 1984-11-02 | 1984-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16665584U JPS6183344U (en) | 1984-11-02 | 1984-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6183344U true JPS6183344U (en) | 1986-06-02 |
Family
ID=30724465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16665584U Pending JPS6183344U (en) | 1984-11-02 | 1984-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6183344U (en) |
-
1984
- 1984-11-02 JP JP16665584U patent/JPS6183344U/ja active Pending