JPS6184033A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent generation of disconnection of wire at the stepped part of the second layer wiring by a method wherein an interlayer insulating film is thinly formed at the penetrated hole part, and the degree of stepping is reduced when the penetrated hole is formed. CONSTITUTION:An SiO2 film 2 is grown in vapor phase on the semiconductor substrate 1 whereon a connection hole 10 is provided, and the above material is tapered by performing an etching with an HF liquid using a photoresist mask. The mask is removed, and a protruded trapezoidal SiO2 film 2 is left at the penetrated hole formed part. Then, the first wiring 3, an interlayer insulating film 4 and a photoresist 5 are superposed thereon. A dry etching is performed under the condition wherein the etching rates of the photoresist 5 and the interlayer insulating film 4 are equal, the surface of the insulating film 4 on the penetrated hole and other part is flattened, and the residual resist is removed. Lastly, an aperture 19 is provided, a wiring 6 is formed and a protective film 7 is coated thereon. According to this constitution, the disconnection of wire of the wiring 6 can be prevented. Also, as the interlayer insulating film 4 is thickly formed on the region other than the penetrated hole 19, the interlayer capacitance can be maintained small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device with improved multilayer wiring structure.

[Prior Art] Conventionally, in a semiconductor device having a multilayer wiring structure, in order to form a through hole connecting a first wiring and a second wiring on a semiconductor substrate, as shown in FIG. All wiring @1 is formed on the insulating layer 8 formed above, and then an interlayer insulating film 4 is formed on the entire surface of the semiconductor substrate, and after smoothing the steps by applying silica film, etc., a photoresist is masked. This was done by removing part of the interlayer insulating film using a wet or dry process. In FIG. 1, 6 is a second wiring, 7 is a cover film, and 9 is a through hole.

[Problem to be Solved by the Invention J] In the multilayer wiring of the conventional semiconductor device described above, in order to reduce the inter-wiring capacitance between the first wiring and the second wiring, it is necessary to increase the thickness of the interlayer insulating film. However, as shown in FIG. 2, there was a problem in that the level difference in the through-hole portion became large and the second wiring was broken at the through-hole portion. The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which the above-mentioned step difference in the through-hole portion is reduced while keeping the inter-wiring capacitance small.

[Means for Solving the Problems] In the semiconductor device of the first aspect of the present invention, a first wiring is formed on an insulating layer on a semiconductor substrate, and a second wiring is formed by completely covering an interlayer insulating film. In a semiconductor device having a multilayer wiring in which two wirings are connected by through holes formed in an interlayer insulating film, the first insulating layer has a convex trapezoid shape only in the through hole region. Calculation 1: The surface of the interlayer insulating film between the second wirings is flat even on the convex trapezoidal insulating layer, and the thickness of the interlayer insulating film at the through-hole part is thinner than the others. Constructed as a feature.

In addition, the method for manufacturing a semiconductor device according to the second invention of the present invention includes:
A process of forming a vapor phase grown oxide film on a semiconductor substrate with an insulating layer formed on the surface, and taper etching to remove the photoresist gold formed on the through hole forming area, and forming a convex trapezoidal vapor phase on the through hole forming area. A step of leaving a grown oxide film, a step of forming a first wiring, a step of forming an interlayer insulating film, a step of applying a photoresist or silica film on the entire surface of the interlayer insulating film, and a step of applying the photoresist or silica film to the entire surface of the interlayer insulating film. A step of plasma etching the interlayer insulating film in a trench where the through-hole forming area and other areas are substantially flat under conditions such that the etching rate of the interlayer insulating film is equal, so that the surface is flat and the through-hole is formed. The entire feature is that an interlayer insulating film is formed which is thinned only in a region.

[Example J] Next, the present invention will be described with reference to the drawings. 1st
Figures (a) to (d) are cross-sectional views shown in order of steps to explain the structure and manufacturing method of one embodiment of the present invention.

First, as shown in FIG. 1(a), a silicon oxide film 2 is grown by vapor phase epitaxy on a semiconductor substrate 1 on which an insulating layer 8 is formed and a contact hole 10 is formed in the insulating layer 8. The silicon oxide film 2 is taper-etched using a hydrofluoric acid-based etching solution using the photoresist as a mask, and then the photoresist is removed, leaving a convex trapezoidal silicon oxide film 2 in the through-hole forming region. At this time, the silicon oxide film formed by vapor phase growth has a higher etching rate than a silicon oxide film formed in an oxidation furnace or a silicon nitride pattern, so the effect on the underlying layer is small.

Next, as shown in FIG. 1 (bl), a first wiring 3 is formed, and then an interlayer insulation film 4 is grown.Furthermore, a photoresist 5 is applied on the interlayer insulation film 4.

Next, as shown in FIG. 1C, the photoresist 5 and the interlayer insulating film 4 are dried under conditions such that the etching rate is equal to that of the interlayer insulating film 4 until the through-hole area and other parts of the interlayer insulating film become almost flat. Etching. After that, the remaining photoresist gold is removed.

Next, as shown in FIG. 1(d), a through hole 19 is opened, a second wiring 6tl- is formed, and then a cover film 7
After forming, the semiconductor device of this example is completed.

Note that if the level difference due to the first wiring thickness is large, the first
It is also possible to flatten the state shown in Figure (c) by using a silica film coating or the like.

[Effects of the Invention] As explained above, in the present invention, the thickness of the interlayer insulating film only in the through-hole portion can be made thinner, so the step difference when forming the through-hole becomes smaller, and the second wiring can be formed in the through-hole portion. Prevents cutting. Further, since the thickness of the interlayer insulating film other than the through-hole portion is thick as in the conventional case, the inter-wiring capacitance can be kept small. In addition, since the surface of the interlayer insulating film is formed to be substantially flat, it can have a great effect in improving the reliability of wiring as well as improving step portions.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are cross-sectional views shown in the order of steps for explaining the structure and manufacturing method of one embodiment of the present invention;
The figure is a cross-sectional view of an example of a semiconductor device having a conventional multilayer wire structure. 1... Semiconductor substrate, 2... Vapor phase growth (
silicon) oxide film, 3...first wiring, 4...
...Interlayer insulating film, 5...Photoresist, 6
...Second wiring, 7...Cover membrane, 8
...Insulating layer, 9.19...Through hole, 10...Contact hole. , No゛q, 2 sweat゛(-1) (Shin (Dano 1st dormitory zTiJ

Claims (2)

[Claims] (1) A first wiring is formed on an insulating layer on a semiconductor substrate, a second wiring is formed through an interlayer insulating film, and the first and second wiring are connected through a through hole formed in the interlayer insulating film. In the semiconductor device having multilayer wiring, the insulating layer under the first wiring has a convex trapezoidal shape only in the through-hole region, and the surface of the interlayer insulating film between the first and second wirings has the convex trapezoidal shape. 1. A semiconductor device characterized in that a trapezoidal insulating layer is flat compared to others, and the thickness of an interlayer insulating film in a through-hole part is thinner than others. (2) Forming a vapor phase grown oxide film on a semiconductor substrate with an insulating layer formed on the surface, and taper etching using the photoresist formed on the through-hole formation area as a mask to form a convex trapezoid in the through-hole formation area. A step of leaving a vapor-phase grown oxide film, a step of forming a first wiring, a step of forming an interlayer insulating film, a step of applying a photoresist or silica film on the entire surface of the interlayer insulating film, and a step of applying the photoresist or silica film to the entire surface of the interlayer insulating film. a step of plasma etching the interlayer insulating film under conditions such that the etching rate of the film and the interlayer insulating film are equal to each other until the through hole forming area and other areas thereof are substantially flat, and the surface is flat and the through hole is formed. 1. A method of manufacturing a semiconductor device, comprising forming an interlayer insulating film that is thinned only in a forming region.