JPS6184059A - solid-state imaging device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a solid-state imaging device in which a light-receiving element made of a static induction transistor (SIT) having a non-destructive amplification/reading function and its peripheral circuitry are provided on the same chip. It is something.

(Prior art) A solid-state imaging device in which an SIT as a light-receiving element and its peripheral circuit are formed on the same chip was proposed by the applicant in Japanese Patent Application No.
It is proposed in No. 85904. Figure 2 shows its configuration, in which an SIT for light reception and an NMO3F-T for peripheral circuits are formed on the same chip.
2 is the NMO3FET part for the peripheral circuit, and 2 is the light receiving SfT.
The P well 3 and the P-substrate 4 for the S F B T are electrically isolated from each other by a buried N layer 5 and an N-epitaxial layer 6. In this solid-state imaging device, the light receiving SIT
The source 7 and drain 8 of the
It has the advantage that the gate electrode 13 of NMOS FBT and the gate electrode 14 of NMOS FBT can be formed in the same process.

However, in the solid-state imaging device shown in FIG. 2, the peripheral circuit is formed only with NMO5FETs, so
There were the following problems specific to the SFET circuit.

■Higher power consumption than CMO5FET.

■If the shift register is made of NMO3FBT, a booster circuit such as a bootstrap is required.

■Compared to a circuit using CMO5FBT, the characteristics of the analog switch are inferior, leading to a decrease in linearity and dynamic range.

■Compared to CMO3FBT, the circuit configuration using only NMO3FET is complicated.

(Object of the Invention) An object of the present invention is to provide a solid-state imaging device that solves the above-mentioned problems.

(Summary of the Invention) A solid-state imaging device of the present invention includes a light-receiving element consisting of a horizontal electrostatic induction transistor having a source, a drain, and a gate on its surface or a vertical electrostatic induction transistor having an insulated gate structure on its surface, and an insulated gate. The device is characterized in that a peripheral circuit consisting of complementary field effect transistors having a structure is provided on the same chip.

(Example) In carrying out the present invention, there are two cases: (1) to form the channel part of the SIT by an epitaxial process, and (2) to form it by a thermal diffusion method. There are cases where a buried layer for substrate isolation is formed and cases where it is not.

Hereinafter, the above-mentioned four embodiments will be described in which the SIT is a horizontal type having a source, drain, and gate on the surface (hereinafter referred to as LSIT). In the following examples, the LSIT is an N-channel device in which the source/drain current flows by electrons, the gate structure is a MOS type, and the semiconductor substrate is an S
This will be explained as i.

First Embodiment In the first embodiment, the channel portion of the LSIT is formed by a thermal diffusion method, and there is no N type buried layer under the CMOS FET forming portion. The configuration of this solid-state imaging device will be described below with reference to process diagrams shown in FIGS. 1A to 1F.

First, in FIG. 1A, P-, P-/P- or P-
/P epitaxial substrate (P- thickness is 10 μm or more, P- concentration is IXl013cm-3 or less) 21, a resist 22 is applied, and the N for PMOSFET is applied.
A well window 23 is formed by photolithography, and arsenic, phosphorus, or the like is implanted in an amount of about 1×10 12 cm −2 by ion implantation.

Next, in FIG. 1B, a resist 24 is applied again onto the substrate 21, and a window 25 for an LSIT N channel is formed.
It is formed by IJ lithography, and N-type impurities such as arsenic and phosphorus are added by ion implantation.
Inject about m-2. Note that in the first N8, 26 is an N type impurity implantation layer for forming an N well.

Next, an N-well drive-in will be held. Figure 1 C is this N
In the picture after the Wel Drive-in, 27 is P M
N well for OS F B T, 28 is N well for LSIT
Represents the channel part. As N-Well Drive-in,
Heat treatment was performed at a temperature of 1200°C for 10 to 20 hours, and p
N well 27 for Mo 5FET with surface concentration 1~5X1
015cm-3 to a junction depth of about 8 to 13μm, and the N layer 28 for the LSIT channel is formed at a surface concentration of IXl0.
13-5 XIO13am-' Formed at a junction depth of approximately 5-8 μm.

Next, in the first drawing, a resist 29 is applied, and a window 30 for NMO5FBT is formed by photolithography.
Boron is implanted in an amount of approximately 1.4×10 13 cm −3 using an ion implantation method.

FIG. 1E is a diagram after performing the P well drive-in after the above steps, and 31 indicates the P well.

As a P-well drive-in, at a temperature of 1200℃
Heat treatment is performed for ~5 hours to reduce the surface concentration of P well 31 to 1 ~
2×l016 cm−3 and a junction depth of 4 to 5 μm.

FIG. 1F shows that after the above steps, a source 32 and a drain 33 made of an N+ diffusion layer are placed in the N layer 28 for the LSIT channel, a source 34 and a drain 35 made of an N+ diffusion layer are placed in the P well 31, and an N well for the PMO3FBT. A source 36 and a drain 37 made of a P+ diffusion layer are simultaneously formed on 27,
After that, gate insulating films 38, 39, 40 are formed at the same time, gate electrodes 41, 42, 43 are formed at the same time, and N
A light receiving part consisting of MO3LS[T44' and NMO
C of S FET 45 and PMO5FET46
FIG. 3 is a final sectional view configuring a peripheral circuit section made of MO3FET. Here, the distance d between the P-well 31 and the N-well 27 is set to be 4 μm or more, and the breakdown voltage between the P-substrate 21 and the P-well 31 is set to be IOV or more.

In the first embodiment, since an N-type buried layer is not formed, there is an advantage that one mask process can be omitted, and there is also an effect that the concentration of the N layer 28 for the LSIT channel can be accurately determined by the ion implantation process. .

Second Embodiment The second embodiment includes 1. , the channel part of the SIT is formed by an epitaxial layer, and C) there is no N type buried layer under the 110 S F E T forming part. The structure of this solid state imager will be explained below with reference to process diagrams shown in FIGS. 3A to 3F.

First, in FIG. 3A, N is placed on the P- or P substrate 51.
- forming an epitaxial layer 52; This epitaxial layer 52 has a concentration of 1 to 5 Xl013 cm-3 and is grown so that the layer thickness after the process is 5 to 10 μm.

Next, in the third N8, a resist 53 is applied on the epitaxial layer 52, a P layer and an N well window 54 for 105FET are formed by photolithography, and an N type impurity (for example, phosphorus) is added by ion implantation. am-2
Inject some amount.

Next, an N-well drive-in will be held. Figure 3 C is this N
In the diagram after completing Welltribe-in: 55 is PMO
5FET N well is shown, and the epitaxial layer 52 is L
This is an N channel section for SIT. Note that the N well 55 has a surface concentration of 1 to 5 x 1015 cm-3 and a junction depth of 10 μm.
It should be about m.

Next, in the third drawing, a resist 56 is applied on the epitaxial layer 52 and the N-well 55, and a P-well diffusion window 57 is formed by photolithography. Note that the diffusion window 57 on the left side in the third diagram is created to form a P layer that electrically isolates the epitaxial layer 52 and the N well 55. Thereafter, ~1.4
A P-type impurity such as boron is implanted to a depth of about cm-2.

FIG. 3E is a diagram after performing the P well drive-in after the above steps, and 58 indicates the P well.

As a P-well drive-in, the temperature is 1200℃, ~
Heat treatment is performed for 4 hours, and the P well 58 is heated to a surface concentration of 1 to 1.
2XIO"cm-3, and a junction depth of ~4 μm is formed.

FIG. 3F shows that after the above steps, a source 59 and a drain 60 made of an Nₛ diffusion layer are placed in the epitaxial layer 52 that will become the channel portion of the LSIT, and a source 61 and a drain 62 made of an N+ diffusion layer are placed in the N well 55. A source 63 and a drain 64 made of a P layer are simultaneously formed in the P well 58, and then gate insulating films 65, 66 and 67 are formed at the same time, and then gate electrodes 68, 69 and 70 are formed simultaneously to form an NMO5LSIT 71. The light receiving section and P M [
I S P E T 72 and N +, (OS F
FIG. 7 is a final cross-sectional view of the peripheral circuit section including a CλIO3FET of E T 73; Here, P well 5
The distance d between the P substrate 51 and the N well 55 is set to be 4 μm or more, and the breakdown voltage between the P substrate 51 and the P well 58 is set to be IOV or more.

In the second embodiment, LSIT and C1, to S
Since the channel portion of FET is formed as much as the epitaxial layer, it has the advantages of good crystallinity, long lifetime, and low leakage current. Further, since a buried layer is not formed and the N-channel mask in the first embodiment is not required, there is an advantage that the number of mask steps is reduced accordingly.

Third Embodiment In the third embodiment, the channel portion of the LSIT is formed by a thermal diffusion method, and an N-type buried layer is provided under the CMO3FET forming portion. The configuration of this solid-state imaging device will be described below with reference to process diagrams shown in FIGS. 4A to 4G.

First, in FIG. 4A, a resist 82 is applied on a P or P-substrate 81, and a window 83 for the iso-rayon N layer is formed by photolithography. After that, an N-type impurity (for example, phosphorus) is added by ion implantation.
Inject ~I Xl013cm-2.

Next, as shown in FIG. 4B, a P-epitaxial layer 84 is formed.
form. This epitaxial layer 84 preferably has a concentration of 5 Xl012 cm-3 or less and a thickness of 15 to 20
Let it be μm. In addition, in the 4th N8, 85 is a well.
The N layer for substrate isolation is shown.

Next, in FIG. 4C, a resist 86 is applied on the epitaxial layer 84, an N-channel window 87 for LSIT is formed by photolithography, and N-type impurities such as arsenic and phosphorus are implanted by ion implantation. 109~I X10"
Inject about am-2.

Next, in the fourth diagram, a resist 88 is applied on the epitaxial layer 84, and the N-well window 88 for PMO5FIET is coated on the epitaxial layer 84.
9 is formed by photolithography, and an N-type impurity (for example, phosphorus) is implanted in an amount of about 1×10 12 cm −2 by ion implantation. Note that in the fourth diagram, 90 indicates an N layer for forming the LSIT channel N single layer.

Next, in FIG. 4E, a resist 91 is applied, a window 92 for NMO3F[l:T is formed by photolithography, and boron for the P well is filled with 1.4 XIO" am-
Inject about 3 times. In addition, in FIG. 4, 93 indicates an N layer for an N well.

Next, we will have a well drive-in. FIG. 4F is a diagram after completing this well drive-in, in which 94 shows the N layer for LSIT channel, 95 shows the N well, and 96 shows the P well. This well drive-in is carried out at a temperature of 1200° C. for 10 to 15 hours. Here, the surface concentration of the N layer 94 is 1 to 5 XIO'''am-3, the surface concentration of the N well 95 is 1 to 5 3, and the depth of the N well 95 and the P well 96 is 7 to 9 μm, and their lower parts are respectively bonded to the isolation N layer 85 raised by the well heat treatment.The depth of the N layer 94 at this time is is approximately 6 μm.

FIG. 4G shows that after the above steps, a source 97 and a drain 98 made of an N+ diffusion layer are placed in the N layer 94 constituting the LSIT channel section, and a source 99 and a drain 100 made of a P" diffusion layer are placed in the N well 95. A source 101 and a drain 102 made of N diffusion layers are simultaneously formed in the P well 96, and then gate insulating and insulating films 103, 104, and 105 are formed.
are formed at the same time, and then gate electrodes 106.107.1
08 is formed at the same time to form a light receiving section consisting of NMO3LSIT109, PMO3FETI10 and NMO3LSIT109.
FIG. 3 is a final cross-sectional view of the 3FETI 11 and the peripheral circuit section made up of CMO3FETs. As is clear from FIG. 4G, in this example, the P well 96 and the P or P-substrate 8
In order to electrically isolate the P well 96 from the N well 95, the P well 96 is surrounded by an N well 95.

In the third embodiment, the channel portions of the LSIT and the CMO ET are formed of an epitaxial layer, so there is less leakage current, and since the N-channel is formed by ion implantation, the concentration can be easily controlled. Also,
Compared to the case without a buried N layer, the drive-in time of the well can be shortened, and there is an effect of improving crystallinity and controllability.

Fourth Embodiment In the fourth embodiment, the channel portion of the LSIT is formed by an epitaxial method, and an N-type buried layer is provided under the CMIISFBT forming portion. The configuration of this solid-state imaging device will be described below with reference to process diagrams shown in FIGS. 5A to 5F.

First, in FIG. 5A, a resist 122 is applied onto a P or P-substrate 121, and an isolation N wearing window 123 is formed by photolithography.

Thereafter, an N-type impurity (for example, phosphorus) is implanted by lXIQ+2 to lXIO''cm-2 by ion implantation.

Next, as shown in No. 5N8, N-epitaxial M12
Form 4. This epitaxial layer 124 is formed to have a concentration of 1 to 5 Xl013 cm-3 and a thickness of 5 to 10 μm after the process is completed. Furthermore, Figure 5B
In the figure, 125 indicates an N layer for well-substrate isolation.

Next, in FIG. 5C, a resist 126 is applied on the epitaxial layer 124, an N-well window 127 for PMO3FBT is formed by photolithography, and N-type impurities such as arsenic and phosphorus are added by ion implantation.
Inject about 2cm-2.

Next, in the fifth diagram, a resist 128 is applied on the epitaxial layer 124, a P-well window 129 for NMO3FET and isolation is formed by photolithography, and a P-type impurity (for example, boron) is added by ion implantation. About 1 to 2 XIO"cm-' is implanted. In the fifth diagram, 1"5 indicates an N layer for forming an N well.

Next, we will have a well drive-in. FIG. 5E shows (8) after completing this well drive-in, 131 indicates the N well, and 132 indicates the P well. This well drive-in is carried out at a temperature of 1200° C. for 10 to 15 hours. Here, the surface concentration of the N well 131 is 1 to 5×IQIS
cm-3, the surface concentration of P well 132 is 1-2X10
cm −' and C! , Nxle 131 for l03F revision
The depth of the P well 132 is set to 7 to 9 μm, and the lower portion thereof is bonded to the isolation N layer 125 raised by the well heat treatment.

Figure 5F shows the LSIT channel section 1 after the above steps.
24, a source 133 and a drain 134 made of an N'' diffusion layer are placed in the N well 131, a source 135 and a drain 136 made of a P'' diffusion layer are placed in the NMO3FET.
A source 13 made of an N” diffusion layer is placed in the P well 132.
7. Form the drain 138 at the same time, then form the gate insulating films 139, 140, 141 at the same time, and then form the gate electrodes 142, 143, 144 at the same time to form the light receiving part made of N)(O3LSIT145) and the PMO3
CMO3 reference of OTO T146 and NMO3FET147
FIG. 2 is a final sectional view configuring a peripheral circuit section consisting of the following. As is clear from FIG. 5F, in this example, the N well 131
In order to provide electrical isolation between the N-epitaxial layer 124 and the N-epitaxial layer 124, a P-well diffusion layer is inserted between them.

In the fourth embodiment, LSIT and CMO5FET
Since the channel portion is formed of an epitaxial layer, leakage current can be reduced. Furthermore, compared to the case without a buried N layer, the well drive-in time can be shortened, and crystallinity can be improved and controllability can be improved.

It should be noted that the present invention is not limited to the above-described embodiments, and can be modified or changed in many ways. For example, S.I.
T is not limited to MO milk SIT, but also junction and SI
It can also be T, or surface MOS gate vertical S.
It can also be IT. In addition, the device is not limited to the 5ITitN channel device, but can also be made into a P channel portion by changing the impurity type and voltage. Furthermore, although Si was used as the semiconductor in the above example, other semiconductors such as GaAs may also be used.

(Effects of the Invention) As described above, in the present invention, since the SIT as a light receiving element and the CMO5FET constituting its peripheral circuit are provided on the same chip, the following effects can be obtained.

■ Power consumption is lower than when the peripheral circuit is configured with NMOS FBT.

■ Clocked C without using a booster circuit such as a bootstrap with shift lens star! , N in the lO3 circuit!
, (can be formed with an area comparable to that of an OS FET.

-Using CMDS FET improves the characteristics of the analog switch, thus improving linearity and dynamic range.

(2) By providing C to IO3 FETs, various processing and arithmetic circuits can be easily configured. Therefore, it is possible to perform various light reception processing and calculations with a single chip, which is advantageous for making an intelligent IC.

[Brief explanation of the drawing]

1A-F are process diagrams for explaining the first embodiment of the present invention, FIG. 2 is a cross-sectional view of a chip of a solid-state imaging device already proposed by the applicant, and FIGS. 3A-F are process diagrams for explaining the first embodiment of the present invention. Process diagrams for explaining the second embodiment; Figures 4A-G are process diagrams for explaining the third embodiment; Figures 5A-F are process diagrams for explaining the fourth embodiment. It is a diagram. 21, 51.81.121...Substrate 27, 55.95. 131...N well 3L 5
8.96. 132...P well 28, 94...N
One layer 52, 124...Epitaxial layer 32, 34.3
6.59.6163.97.99. 101. 133
゜135, 137... Source 33, 35.37.60.62.64.98. to
o, 102. 134°136, 138...
・Drain 38,' 39.40.65. ' 66, 67, 10
3. 104. 105. 139°140, 141・
...Gate insulating film 41, 42. 43. 68. 69. 70. 1
06. 107. 108. 142°143, 144
...gate electrodes 44, 71. ．． 109. 145...NMO3
LSIT45, 73. 111. 147...NMO
3FET46, 72. 110. 146...PM
OS F E T Fig. 1 44 4.5 '6 2nd
Figure 1

Claims (1)

[Claims] 1. A light receiving element consisting of a horizontal electrostatic induction transistor having a source, drain, and gate on its surface or a vertical electrostatic induction transistor having an insulated gate structure on its surface, and a peripheral circuit consisting of a complementary field effect transistor having an insulated gate structure. What is claimed is: 1. A solid-state imaging device, characterized in that: and are provided on the same chip.