JPS6184697U - - Google Patents

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Publication number
JPS6184697U
JPS6184697U JP14696985U JP14696985U JPS6184697U JP S6184697 U JPS6184697 U JP S6184697U JP 14696985 U JP14696985 U JP 14696985U JP 14696985 U JP14696985 U JP 14696985U JP S6184697 U JPS6184697 U JP S6184697U
Authority
JP
Japan
Prior art keywords
voltage
inverter
current
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14696985U
Other languages
Japanese (ja)
Other versions
JPS6233520Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14696985U priority Critical patent/JPS6233520Y2/ja
Publication of JPS6184697U publication Critical patent/JPS6184697U/ja
Application granted granted Critical
Publication of JPS6233520Y2 publication Critical patent/JPS6233520Y2/ja
Expired legal-status Critical Current

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  • Control Of Ac Motors In General (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案が適用する電流形インバータに
よる電動機の駆動運転法を示す場合の駆動系の一
具体例、第2図はそれを簡素化した場合の直流リ
アクトルを含んだ電動機系のブロツク構成図、第
3図は電圧制御用増幅器と電流制御用増幅器の具
体的な構成を示す回路図、第4図は第1図(第2
図)の駆動系の伝達関数を示すブロツク構成図、
第5図はその伝達関数の特性方程式より根を導び
き出しゲインによつて根の軌跡がどの様に変化す
るかを複素平面上で示した根軌跡図、第6図は本
考案によるゲインを調整する場合の具体例を示す
実施例、第7図は誘導電動機の任意の相の一次電
流波形図、第8図は第4図を変形した場合の伝達
関数のブロツク構成図、第9図は第2図を具体化
した場合の制御系全体の伝達関数のブロツク構成
図。 CVは順変換部、IVは逆変換部、Ldは直流
リアクトル、OPは電圧制御用増幅器、OP
は電流制御用増幅器、Aは電圧検出回路、BはV
/F変換回路、Cは移相回路、RCはリングカウ
ンタ、IMは誘導電動機、1及び3は乗算回路、
2は除算回路。
Fig. 1 is a specific example of a drive system showing the driving operation method of a motor using a current source inverter to which the present invention is applied, and Fig. 2 is a simplified block configuration of the motor system including a DC reactor. Figure 3 is a circuit diagram showing the specific configuration of the voltage control amplifier and current control amplifier, and Figure 4 is the circuit diagram shown in Figure 1 (Figure 2).
A block configuration diagram showing the transfer function of the drive system in Fig.
Figure 5 is a root locus diagram that derives the roots from the characteristic equation of the transfer function and shows how the root locus changes depending on the gain on the complex plane, and Figure 6 shows the gain according to the present invention. An example showing a specific example of adjustment, Fig. 7 is a primary current waveform diagram of any phase of the induction motor, Fig. 8 is a block diagram of the transfer function when Fig. 4 is modified, and Fig. 9 is a diagram of the block diagram of the transfer function. FIG. 2 is a block configuration diagram of the transfer function of the entire control system when FIG. 2 is embodied. CV is a forward conversion section, IV is an inverse conversion section, Ld is a DC reactor, OP 1 is a voltage control amplifier, OP 2
is the current control amplifier, A is the voltage detection circuit, and B is the V
/F conversion circuit, C is a phase shift circuit, RC is a ring counter, IM is an induction motor, 1 and 3 are multiplication circuits,
2 is a division circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧設定信号と電圧検出信号との偏差分を増幅
して電流指令を与える電圧制御ループと、前記電
流指令信号と電流検出信号との偏差分を増幅した
信号を基に順変換部のゲートを制御する電流制御
ループと、前記電圧設定信号を基に逆変換部のゲ
ートを制御して出力周波数を制御する周波数制御
ループとを備え、速度検出信号をフイードバツク
しない電流形インバータで負荷電動機を駆動する
ものにおいて、インバータの動作周波数ω又は
インバータの交流出力電圧Eaの逆数を取る割算
器と、この割算器の出力と前記電圧制御ループの
電圧制御用増幅器の出力とを掛算して、前記電流
制御ループに電流指令として与え、且つインバー
タ制御系の総合ゲインを略一定にする掛算器とを
具備したことを特徴とする電流形インバータの制
御装置。
A voltage control loop that amplifies the deviation between the voltage setting signal and the voltage detection signal to provide a current command, and controls the gate of the forward conversion section based on the signal that amplifies the deviation between the current command signal and the current detection signal. and a frequency control loop that controls the output frequency by controlling the gate of the inverse converter based on the voltage setting signal, and drives the load motor with a current source inverter that does not feed back the speed detection signal. , a divider takes the inverter's operating frequency ω 0 or the reciprocal of the inverter's AC output voltage Ea, and the output of this divider is multiplied by the output of the voltage control amplifier of the voltage control loop to obtain the current. 1. A control device for a current source inverter, comprising a multiplier that provides a current command to a control loop and makes the overall gain of an inverter control system substantially constant.
JP14696985U 1985-09-26 1985-09-26 Expired JPS6233520Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14696985U JPS6233520Y2 (en) 1985-09-26 1985-09-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14696985U JPS6233520Y2 (en) 1985-09-26 1985-09-26

Publications (2)

Publication Number Publication Date
JPS6184697U true JPS6184697U (en) 1986-06-04
JPS6233520Y2 JPS6233520Y2 (en) 1987-08-27

Family

ID=30705208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14696985U Expired JPS6233520Y2 (en) 1985-09-26 1985-09-26

Country Status (1)

Country Link
JP (1) JPS6233520Y2 (en)

Also Published As

Publication number Publication date
JPS6233520Y2 (en) 1987-08-27

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