JPS61854A - Input and output controller - Google Patents

Abstract

PURPOSE:To attain the independent actions or coupled actions according to the length of a single record unit of a controller by providing the 1st and 2nd buffer memories, a buffer memory address register and a buffer memory control register. CONSTITUTION:A CPU40 is connected to a ROM42, a RAM41, address buffer registers 21 and 31 and buffer memory control registers 22 and 32 respectively via a bus 50. Then the CPU40 can perform read and write to registers 21 and 31 as well as 22 and 32. The 1st buffer memory 20 is connected to the registers 21 and 22, a write data selector 44 and a read data buffer register 23. While the 2nd buffer memory 30 is connected to the registers 31 and 32, the selector 44 and a read data buffer register 33. A selector 43 supplies registers 23 and 33 and transmits the data of both registers 23 and 33 to a magnetic tape device 5 via a bus 11 as well as to a channel device 1 via a bus 10. The selector 44 selects buses 10 and 11 and sends the data of these buses to memories 20 and 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an input/output control device, and particularly to a buffer memory control method.

[Prior art]

An input/output control device generally has a buffer memory inside it, but the capacity of the buffer memory is limited to one of the devices to be controlled.
It must correspond to the recording rate position length. Therefore, the capacity of the buffer memory is the maximum length of one recording rate among the five devices to be controlled, but if the capacity is less than that, a plurality of buffer memories will be required. However, if the length is adjusted to the maximum length of one recording rate, there will be parts that are not used when controlling equipment with a unit length smaller than that, which is generally wasteful and also causes a large loss of time. In addition, when using a plurality of devices, the conventional method requires switching at high speed within the transfer time, which is not only an economic burden due to switching circuits, but also technically complex.

[Purpose of the invention]

The present invention has been proposed in view of the above-mentioned problems of the conventional example, and provides a plurality of buffer memories that can be operated independently or in combination depending on the length of one recording rate of a control device. The purpose is to provide an input/output control device with

[Structure of the invention]

The present invention includes a first buffer memory, a tenth register (sofa memory address register) indicating a storage address of the first buffer memory, and a first register (sofa memory address register) that holds control information for controlling the first buffer memory. a memory control register, a second buffer memory, a second buffer memory address register indicating a storage address of the second buffer memory, and a second buffer memory control holding control information for controlling the second buffer memory. a register, and according to the first buffer memory control register and the first buffer memory address register conditions, the information in the first buffer memory control register is transferred to the buffer memory control register of M2, and the The first buffer memory and the second buffer memory can be operated in a connected manner or can be operated independently by writing specific information to the first buffer memory control register.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a system including a human output control device according to an embodiment of the present invention. The channel device l is connected to the input/output control devices 4 and 6 via a bus line 10. The input/output control device f4 is a magnetic tape control device, and the path line 1
1, a magnetic tape unit [5 (hereinafter abbreviated as MTU) is controlled. The input/output control device 6 is a line printer control device and controls the line printer 7. Central processing unit 2
extracts, decodes, and executes instructions stored in the main memory 3. That is, if the command is an input/output command, the Nayanel device 11k is activated, and the activated channel device 1 retrieves the command from the main storage device 3 and sends it to a specific input/output control device. Thereafter, the channel device 1 starts data transfer with the nuclear input/output control device.

The input/output control device 4 will be explained below as an example. FIG. 2 is a block diagram of the data bus relationship of the input/output control device 4. Microprocessor 40 is connected via CPU path 50 to read-only memory 42 . Read/write memory 41, buffer memory address registers 21, 31 . Connected to buffer memory control register 22.32. MicroProcera? -4o is buffer memory address register 21.31 and buffer memory control register 22゜3
2, it is possible to read and write. The first buffer memory 20 has a buffer memory address register 21 . Buffer memory control register 22.
Write data selector 44 and read data rose 2
It is connected to the register 23. The second buffer memory 30 has a buffer memory address register 31 . Buffer memory control register 32. It is connected to the write data selector 44 and the read data buffer register 33. The read data selector 43 inputs the read data buffer registers 23 and 31, and sends the data to the MTU 5 via the bus line 11 and passes #! 10 to the channel device 1.

The write data selector 44 is set to bus line 10 or bus line 1.
Select 1 and buffer the data on the path 20.3
Send to 0. FIG. 3 is a more detailed block diagram of the input/output control device shown in FIG. 2.

First, the first buffer memory 20 will be explained. Buffer memory read request holding flip-flop 3 from channel
00 is connected to the AND circuit 104.204 via the signal line 304.
connected to. The buffer memory write request holding flip-flop 301 from the channel connects the write data selector 44° to the AND circuit 105, 2 via the signal 1i1305.
It is connected to 05. The buffer memory read request holding flip-flop 302 from the MTU is connected to the signal line 306.
It is connected to AND(2) path 106.206 via. A buffer memory write request holding clip frog 303 from the MTU is connected to a write data selector 44° AND circuit 107, 207 via a signal line 307.

The selector 109 selects either data from the CPU path 50 or fixed data, and sets the data in the Batzer memory control register 22. The control register 22 is a flip-flop (hereinafter abbreviated as FF) 320°111.1
It consists of 12, 113, 114. F F 320 outputs a connection control signal for the buffer memories 20 and 30, and is connected to the AND circuit 321 via the signal line 309. FFIII outputs a read control signal for the channel device 1, and is connected to the AND circuit 1 via the signal line 152.
04. Connected to selector 209. The FF 112 outputs a write control signal for the channel device, and is connected to the AND circuit 105 . Connected to selector 209.

The FF 113 outputs a read control signal from the MTU 5, and is connected to the AND circuit 106 via a signal line 154ik.
, are connected to the selector 209. FF114 is MTU5
This outputs the write control signal from the signal line 1.
AND circuit 107 . Connected to selector 209. AND circuit 104 is connected to OR circuit 102 via signal line 156. AND times %105 is signal m158
Continued through LOFt times N103 KIl. The AND circuit 106 connects ORti1Mio2Kt via the signal line 157.
i will be continued. AND circuit 107 connects O via signal line 159.
Connected to R circuit 103.

The OR circuit 102 is connected to the buffer memory control circuit 100 . AND circuit 101. It is connected to the read data selector 43. OR circuit 103 is connected to buffer memory control circuit 100 via signal line 161. The buffer memory address register 21 is the buffer memory 2
This is an increment register indicating the address of data stored in 0, and data can be set by the CPtJ pass 50. Further, address information is sent to the buffer memory control circuit 100 through a signal line 150. Furthermore, when a carry occurs as a result of stepping, the AND circuit 321
send a signal to. Buffer memory control circuit 100 controls buffer memory 20. Address information is sent to the buffer memory 20 via the signal line 151, and a write instruction signal is sent via the signal 111j162. Also, during a read operation, a latch timing signal for single-read data is sent to the AND circuit 101 via the signal line 163. Furthermore, although not shown in FIG. 3, flip-flops 300, 30
Various control signals such as 1, 302, and 303 reset signals are also generated and distributed as necessary. The buffer memory 20 is a temporary data storage unit when data is transferred from the channel device 1 to the MTU 5 or when data from the MTU 5 is transferred to the channel device 1. Data read from buffer memory 20 is held in read data buffer register 23 via signal i 164. AN
D circuit 101 is connected to read data buffer register 23 via signal line 165.

Signal @165 is for latching data on signal line 164 into buffer register 23. Read data buffer register 23 is connected to read data selector 43 via signal line 166. The read data selector 43 is connected to the signal line 166 by the signal line 160 or the signal line 260.
The data on the signal line 266 or the data on the signal line 266 is selected. The selected data is transferred to the channel device 1 via the bus line 10.
or to the MTU 5 via the bus line 11.

The write data selector 44 selects data on the bus line 10 or data on the bus line 11 using the signal line 305 and the signal line 307. The selected data is on the signal line 311
Sent to Nasuke Buff Amezori 20.30. The AND circuit 321 is connected to the buffer memory control registers 22, 32 and the selectors 109 and 209 through the signal line 308. When the AND circuit 321 is established, the data in the buffer memory control register 22 is set in the Batza memory control register 32, and then fixed data (cello in the embodiment) is set in the buffer memory control register 22.

The configuration of the second buffer memory is FF329 and AND
They are the same except for the circuit 321, and a completely similar explanation can be made by replacing 1× with 2× or IXX with 2×× in the explanation of the first buffer memory.

Next, the operation when writing from the channel device 1 to the MTU 5 of the input/output control device according to this embodiment will be explained.

In the case of a general data length, the input/output control device 4 receives a command for writing a general data length. Then, the microprocessor-40 shown in figure M2 is the CPU
Set FF112 in the 1s3 diagram via bus 5o, and
F320゜111.113, 114.211~214
Reset.

The buffer memory address registers 21 and 31 are also reset. After that, when the buffer memory write request FF 301 from the channel is set, the data on the bus line lo is selected from the signal line 305iC, the AND circuit 105 is established, and the buffer memory control circuit 100 is activated. The buffer memory control circuit 100 stores the data on the signal line 311 in the buffer memory 20 according to the address indicated in the buffer memory address register 21. Thereafter, the buffer memory address register 21 is incremented. Thus 1
The record length data is input into the buffer memory 2o. Then, the processor 40 sets FF113 and FF212, and sets FF320.111.1!2,114,211°2.
13.214 Reset. Also, at the same time as resetting the buffer memory address registers 21 and 31, M
Start up TU5. Even if the buffer memory write request FF 301 from the channel is set, data is not stored in the buffer memory 2o this time, but data from the channel is stored in the buffer memory 3o in the same manner as described above.

Furthermore, when the read request FF 302 from the MTU 5 is set, the AND circuit 106 is established, and therefore the OR@ path 102
is established and the buffer memory control circuit 100 is activated.

The buffer memory control circuit 100 reads data from the buffer memory 2o according to the address indicated by the buffer memory address register 21. Then, within the read time, a signal is sent to the signal line 163 and the AND circuit 101
is established, and the read data from the buffer memory 20 is set in the read data buffer register 23. Thereafter, the buffer memory address register 21 is incremented.

The selector 43 sends the data on the signal #166 via the bus line 11 to the MTU 5 using the signal line 160, and records it on the tape. The operation of storing data in the buffer memory 3o and the operation of reading data from the buffer memory 2o are performed in parallel, so that data transfer is processed at high speed. Buffer memory 1J20 becomes empty and buffer memory 30
When one record length of data is stored in , the data is read from the buffer memory 30 and sent to the MTU 5, and the data from the channel device is stored in the buffer memory 20.

In the case of writing with the maximum recording length, the input/output control device 5 receives a command indicating that the writing is with the maximum recording length. The microprocessor 40 sets FF320 and FF112 in FIG.
．． 113, 114, 211-214 are reset. It also resets the buffer memory address registers 21.31. After that, when the buffer memory write request FF 301 from the channel is set, data from the channel device is stored in the buffer memory 20 in the same manner as a general data length write operation. However, before one recording length is completely stored in the buffer memory 20, a carry occurs from the buffer memory register 21. When this carry occurs, the ANDli path 321 is established, and the information in the rose 2 memory control register 22 is set in the buffer memory control register 32 via the signal line 308. Thereafter, fixed data zero is set in the buffer memory control register 22.

That is, the control register 22 is cleared. After that, when the buffer memory write request FF 301 from the channel is set, continuous data in the buffer memory 20 is stored in the buffer memory 30. When the storage of data for one record length is completed, set FF320 and FF113, and
111, 112, 114, 211-214. The buffer memory address register 21.31 is reset and MT05 is activated.

When the read request FF302 from the MTU5 is set, data is read from the buffer memory 2o, and the MTU5
sent to. When a carry is output from the buffer memory address register 21, the AND circuit 321 is established, the data in the buffer memory control register 22 is set in the buffer memory control register 32, and the buffer memory control register 22 is cleared. Thereafter, the data in the buffer candy 30 is sent to the MTU 5.

The operation when writing from channel device 1 to MTU5 has been described above, but reading from MTυ5 and writing to channel device jt
It is obvious that the operation of transferring data to 1 can be performed in the same manner. Also, when transferring from the first buffer memory 20 to the second buffer memory 30, carry from the buffer memory at)/threster 21 is used, but
It is obvious that this can be realized under other conditions as well. It is also obvious that after the data in the buffer memory control register 22 is set in the buffer memory control register 32, a specific pattern, such as a transition flag bit, can be set in the buffer memory control register 22. Furthermore, in the embodiment, the case where there are two buffer memories has been described, but the maximum recording length is three times the general recording length.

If it is 4 times as long as the first buffer memory, use 2
It is also obvious that this can be realized by providing three buffer memories, cascading them, and connecting one equivalent to the second buffer memory last.

As explained above, the present invention connects the first buffer memory and the second buffer memory only when the maximum recording length is rarely used, and connects the first buffer memory and the second buffer memory when the recording length is frequently used. Since the two buffer memories can each operate independently, there is no need to have a large buffer memory with a maximum recording length, which is economical. In addition, technically complex control to switch between two low-capacity buffer memories at high speed within a transfer unit time is no longer required, and a circuit for switching between buffer memories is also no longer required.
This has the effect of making it possible to design an input/output control device easily and economically.

[Brief explanation of the drawing]

gt diagram is a schematic configuration diagram of a system including an input/output control device according to an embodiment of the present invention, FIG. 2 is a block diagram related to a data bus of the input/output control device according to an embodiment of the present invention, and FIG. FIG. 2 is a detailed block diagram of an input/output control device according to an embodiment of the invention. 1...Channel device 2...Central processing unit 3...Main storage device 4.6...I/O control device 5...Magnetic tape device 7...Line printer 20.30...Buffer Memory 21.31...Buffer memory address register 22
．． 32...Buffer memory control register 23.24.
...Buffer register 43, IO2, 209...Selector 44...Write data selector 111-114,211-214.300-303...
·flip flop.

Claims (1)

[Claims] A first buffer memory, a first buffer memory address register indicating a storage address of the first buffer memory, and a first buffer memory holding control information for controlling the first buffer memory. a control register, a second buffer memory, a second buffer memory address register indicating a storage address of the second buffer memory, and a second buffer memory control register holding control information for controlling the second buffer memory. and according to the conditions of the first buffer memory control register and the first buffer memory address register, the first
transfer the information in the buffer memory control register to the second buffer memory control register, and write specific information to the first buffer memory control register, thereby controlling the first buffer memory and the second buffer memory. An input/output control device that can operate in conjunction with each other or independently.