JPS6185843A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6185843A JPS6185843A JP59208619A JP20861984A JPS6185843A JP S6185843 A JPS6185843 A JP S6185843A JP 59208619 A JP59208619 A JP 59208619A JP 20861984 A JP20861984 A JP 20861984A JP S6185843 A JPS6185843 A JP S6185843A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- polycrystalline silicon
- point metal
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000002844 melting Methods 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 230000008018 melting Effects 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E50/00—Technologies for the production of fuel of non-fossil origin
- Y02E50/30—Fuel from waste, e.g. synthetic alcohol or diesel
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体装置の高融点金
属あるいはそのクリサイドを電極配線に用いた構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure of a semiconductor device in which a high melting point metal or its crystallized material is used for electrode wiring.
第２図（ａ）、（ｂ）はそれぞれ従来の配線簿造を説明
するだめの半導体装置の瑯１面図であり、１はシリコン
基板、２はフィールド酸化膜、３はゲート酸化膜、４は
多結晶シリコン、５は高融点金属あるいはそのシリサイ
ドである。ところで高融点金属あるいはそのシリサイド
５は後の工程の熱処理により多結晶シリコン５を通り抜
は酸化膜２．３に達する（第２図（ｂ））。フィールド
酸化膜２は厚いので高融点金Ｊ５ｉまたはそのシリサイ
ドによる影響はほとんどないが、ゲート酸化膜３は薄い
のでダメージを受は膜質が劣化し、半導体装置の信頼性
の低下の原因となっていた。FIGS. 2(a) and 2(b) are one-sided views of a semiconductor device for explaining the conventional wiring board construction, respectively, in which 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, and 4 is polycrystalline silicon, and 5 is a high melting point metal or its silicide. By the way, the high melting point metal or its silicide 5 passes through the polycrystalline silicon 5 and reaches the oxide film 2.3 by heat treatment in a later step (FIG. 2(b)). Since the field oxide film 2 is thick, it is hardly affected by the high melting point gold J5i or its silicide, but the gate oxide film 3 is thin, so if it is damaged, the film quality deteriorates, causing a decrease in the reliability of the semiconductor device. .
本発明は上記従来例の欠点に鑑み提案されたものであり
、ゲート酸化膜が高融点金属あるいはそのシリサイドか
らのダメージを受けることのない電極配線構造を有する
半導体装置の提供を目的とする。The present invention has been proposed in view of the above-mentioned drawbacks of the conventional example, and an object thereof is to provide a semiconductor device having an electrode wiring structure in which a gate oxide film is not damaged by a high-melting point metal or its silicide.
本発明は、多結晶シリコンと高融点金属あるいは多結晶
シリコンとシリサイドの複合膜を電極配線として用いる
半導体装置において、活性化領域では前記多結晶シリコ
ンと高融点金属あるいは前記多結晶シリコンとシリサイ
ドの間に絶縁膜を有し、前記多結晶シリコンと高融点金
属あるいは前記多結晶シリコンとシリサイドとの接続は
非活性化領域のみで行われていることを特徴とする。The present invention provides a semiconductor device using a composite film of polycrystalline silicon and a high melting point metal or a composite film of polycrystalline silicon and silicide as an electrode wiring, in an active region between the polycrystalline silicon and the high melting point metal or the polycrystalline silicon and the silicide. The semiconductor device is characterized in that it has an insulating film, and the connection between the polycrystalline silicon and the refractory metal or the polycrystalline silicon and silicide is made only in the non-activated region.
以下図面を参照して本発明を説明する。第１図（ａ）
、 （ｂ）はそれぞれ本発明に係る半導体装置を説明す
るための断面図であり、１はシリコン基板、２はフィー
ルド酸化膜、３はゲート酸化膜、４は多結晶シリコン、
５は高融点金属、あるいはそのシリサイドであシ、１６
は多結晶シリコン４と高融点金属あるいはそのシリサイ
ド５を活性化領域上で分離する絶縁膜である。多結晶シ
リコン４と高融点金属５あるいはそのシリサイドとの接
続は、非活性領域上で行われている（なお活性化領域と
は、ゲート酸化膜が形成されているトランジスタ等の存
在する領域をいう。また非活性化領域とは活性化領域以
外の領域をいい、たとえば実施例で示すようく厚いフィ
ールド酸化膜２が存在する領域をいう。）０そのため後
の熱処理工程を経ても活性化領域上の多結晶シリコンは
その上の絶縁膜により高；Ａ課金＆ｉ ３るいはそのシ
リサイドの浸入によるダメージは阻止され、ゲート酸化
膜の劣化はない（第１図（ｂ））。The present invention will be explained below with reference to the drawings. Figure 1(a)
, (b) are cross-sectional views for explaining the semiconductor device according to the present invention, in which 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is polycrystalline silicon,
5 is a high melting point metal or its silicide, 16
is an insulating film that separates polycrystalline silicon 4 and high melting point metal or its silicide 5 on the active region. The connection between the polycrystalline silicon 4 and the high-melting point metal 5 or its silicide is made on an inactive region (the active region is a region where a transistor, etc., on which a gate oxide film is formed is present). In addition, the non-activated region refers to a region other than the activated region, for example, a region where a thick field oxide film 2 exists as shown in the embodiment. The polycrystalline silicon is prevented from being damaged by the infiltration of silicide by the insulating film thereon, and there is no deterioration of the gate oxide film (FIG. 1(b)).
以上説明したように１本発明によれば活性化領域の多結
晶シリコン上に絶縁膜が存在するため、高融点金属する
いはそのシリサイドの通り抜けを阻止できる。従ってゲ
ート酸化膜の劣化等を防止できるので半導体装置の信頼
性の向上を図ることができる。As explained above, according to the present invention, since the insulating film exists on the polycrystalline silicon in the active region, it is possible to prevent the refractory metal or its silicide from passing through. Therefore, since deterioration of the gate oxide film can be prevented, the reliability of the semiconductor device can be improved.
第１図−）、（ｂ）はそれぞれ熱処理工程前及び後の本
発明の実施例に係る半導体装置の断面崗、第２図（ａ）
、（ｂ）はそれぞれ熱処理工程前及び後の従来例に係る
半導体装置の断面図である。
１・・・シリコン基板
２・・・フィールド酸化膜
３・・・ゲート酸化膜
４・・・多結晶シリコン
５・・・高融点金属あるいはそのシリサイド１６・・・
絶縁膜Figures 1-) and (b) are cross-sectional views of the semiconductor device according to the embodiment of the present invention before and after the heat treatment process, respectively, and Figure 2 (a)
, (b) are sectional views of a conventional semiconductor device before and after a heat treatment process, respectively. 1...Silicon substrate 2...Field oxide film 3...Gate oxide film 4...Polycrystalline silicon 5...High melting point metal or its silicide 16...
Insulating film
Claims (1)
とシリサイドの複合膜を電極配線として用いる半導体装
置において、 活性化領域では前記多結晶シリコンと高融点金属あるい
は前記多結晶シリコンとシリサイドの間に絶縁膜を有し
、前記多結晶シリコンと高融点金属あるいは前記多結晶
シリコンとシリサイドとの接続は非活性化領域のみで行
われていることを特徴とする半導体装置。[Claims] In a semiconductor device using a composite film of polycrystalline silicon and a high melting point metal, or a composite film of polycrystalline silicon and silicide as an electrode wiring, in an active region, the polycrystalline silicon and the high melting point metal or the polycrystalline silicon 1. A semiconductor device comprising an insulating film between silicides, and connection between the polycrystalline silicon and the high melting point metal or between the polycrystalline silicon and the silicide is made only in a non-activated region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208619A JPS6185843A (en) | 1984-10-04 | 1984-10-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208619A JPS6185843A (en) | 1984-10-04 | 1984-10-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6185843A true JPS6185843A (en) | 1986-05-01 |
| JPH0578938B2 JPH0578938B2 (en) | 1993-10-29 |
Family
ID=16559221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59208619A Granted JPS6185843A (en) | 1984-10-04 | 1984-10-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185843A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745967A (en) * | 1980-09-04 | 1982-03-16 | Toshiba Corp | Semiconductor device |
| JPS57122540A (en) * | 1980-12-09 | 1982-07-30 | Fairchild Camera Instr Co | Multilayer metallic silicide mutual wire for integrated circuit |
| JPS5893347A (en) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | Metal oxide semiconductor type semiconductor device and its manufacture |
-
1984
- 1984-10-04 JP JP59208619A patent/JPS6185843A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745967A (en) * | 1980-09-04 | 1982-03-16 | Toshiba Corp | Semiconductor device |
| JPS57122540A (en) * | 1980-12-09 | 1982-07-30 | Fairchild Camera Instr Co | Multilayer metallic silicide mutual wire for integrated circuit |
| JPS5893347A (en) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | Metal oxide semiconductor type semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0578938B2 (en) | 1993-10-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |