JPS6185932U - - Google Patents
Info
- Publication number
- JPS6185932U JPS6185932U JP1984170654U JP17065484U JPS6185932U JP S6185932 U JPS6185932 U JP S6185932U JP 1984170654 U JP1984170654 U JP 1984170654U JP 17065484 U JP17065484 U JP 17065484U JP S6185932 U JPS6185932 U JP S6185932U
- Authority
- JP
- Japan
- Prior art keywords
- delay
- circuit
- delay lines
- inverter
- delaying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案遅延時間補償回路の一実施例を
示すブロツク説明図、第２図はその回路を流れる
波形を示す説明図、第３図は従来の遅延線の一例
を示すブロツク説明図、第４図はその回路を流れ
る波形を示す説明図である。
１，１１，１２：遅延線、２１，２２：インバ
ータ。
FIG. 1 is a block explanatory diagram showing an embodiment of the delay time compensation circuit of the present invention, FIG. 2 is an explanatory diagram showing waveforms flowing through the circuit, and FIG. 3 is a block explanatory diagram showing an example of a conventional delay line. FIG. 4 is an explanatory diagram showing waveforms flowing through the circuit. 1, 11, 12: delay line, 21, 22: inverter.
Claims (1)
くとも二個の遅延線を用いると共に、該遅延線は
、反転器を介して直列に接続して構成されること
を特徴とする遅延線の遅延時間補償回路。 A delay time compensation circuit for a delay line, characterized in that the circuit for delaying a digital signal uses at least two delay lines, and the delay lines are connected in series via an inverter. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984170654U JPS6185932U (en) | 1984-11-09 | 1984-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984170654U JPS6185932U (en) | 1984-11-09 | 1984-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6185932U true JPS6185932U (en) | 1986-06-05 |
Family
ID=30728363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984170654U Pending JPS6185932U (en) | 1984-11-09 | 1984-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185932U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4946366A (en) * | 1972-09-06 | 1974-05-02 | ||
| JPS5783922A (en) * | 1980-11-12 | 1982-05-26 | Fujitsu Ltd | Delay circuit |
-
1984
- 1984-11-09 JP JP1984170654U patent/JPS6185932U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4946366A (en) * | 1972-09-06 | 1974-05-02 | ||
| JPS5783922A (en) * | 1980-11-12 | 1982-05-26 | Fujitsu Ltd | Delay circuit |
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