JPS6185935U - - Google Patents

Info

Publication number
JPS6185935U
JPS6185935U JP17083184U JP17083184U JPS6185935U JP S6185935 U JPS6185935 U JP S6185935U JP 17083184 U JP17083184 U JP 17083184U JP 17083184 U JP17083184 U JP 17083184U JP S6185935 U JPS6185935 U JP S6185935U
Authority
JP
Japan
Prior art keywords
converter
sample point
integration memory
adder
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17083184U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17083184U priority Critical patent/JPS6185935U/ja
Publication of JPS6185935U publication Critical patent/JPS6185935U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図は従来の騒音除去装置を説明するための
ブロツク図、第３図はデイジタル処理形の騒音除
去方法を説明するための波形図である。 １：ＡＤ変換器、２：制御器、４：アドレスカ
ウンタ、１１：積算メモリ、１２：加算器、１３
：レジスタ、１４：割算器、１５，２２：マルチ
プレクサ、１６Ａ，１６Ｂ：波形メモリ、１７Ａ
，１７Ｂ，１８：ゲート。 Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a block diagram illustrating a conventional noise removal device, and Fig. 3 is a waveform diagram illustrating a digital processing type noise removal method. It is. 1: AD converter, 2: Controller, 4: Address counter, 11: Integration memory, 12: Adder, 13
: Register, 14: Divider, 15, 22: Multiplexer, 16A, 16B: Waveform memory, 17A
, 17B, 18: Gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＡＤ変換器と、このＡＤ変換器のＡＤ変換出力
を単位時間長ずつ取込む積算メモリと、この積算
メモリに取込んだ波形データを同一サンプル点ご
とに加算する加算器と、上記積算メモリに取込ん
だ各サンプル点ごとの塁積加算値を加算回数で割
算する割算器とから成る騒音除去装置。 An AD converter, an integration memory that takes in the AD conversion output of this AD converter for each unit time length, an adder that adds the waveform data taken into this integration memory for each same sample point, and and a divider that divides the base product addition value for each sample point by the number of additions.
JP17083184U 1984-11-09 1984-11-09 Pending JPS6185935U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17083184U JPS6185935U (en) 1984-11-09 1984-11-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17083184U JPS6185935U (en) 1984-11-09 1984-11-09

Publications (1)

Publication Number Publication Date
JPS6185935U true JPS6185935U (en) 1986-06-05

Family

ID=30728542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17083184U Pending JPS6185935U (en) 1984-11-09 1984-11-09

Country Status (1)

Country Link
JP (1) JPS6185935U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10311794A (en) * 1997-05-09 1998-11-24 Nippon Telegr & Teleph Corp <Ntt> Scanning emission microscope

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5838028A (en) * 1981-08-28 1983-03-05 Shimadzu Corp A/D converter circuit
JPS58104522A (en) * 1981-12-16 1983-06-22 Nippon Denso Co Ltd Analog-to-digital conversion method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5838028A (en) * 1981-08-28 1983-03-05 Shimadzu Corp A/D converter circuit
JPS58104522A (en) * 1981-12-16 1983-06-22 Nippon Denso Co Ltd Analog-to-digital conversion method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10311794A (en) * 1997-05-09 1998-11-24 Nippon Telegr & Teleph Corp <Ntt> Scanning emission microscope

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