JPS6186888U - - Google Patents
Info
- Publication number
- JPS6186888U JPS6186888U JP17271484U JP17271484U JPS6186888U JP S6186888 U JPS6186888 U JP S6186888U JP 17271484 U JP17271484 U JP 17271484U JP 17271484 U JP17271484 U JP 17271484U JP S6186888 U JPS6186888 U JP S6186888U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power
- counter
- counter circuit
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
Landscapes
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
Description
図示した回路は、本考案のカウンター装置の一
実施例である。
主な図番の説明、１……電池、２……電源スイ
ツチ、５……発光ダイオード、６……フオトカプ
ラー、９……フオトトランジスター、１２……ス
イツチングトランジスター、１４……パルス信号
発生回路、１５……カウンター回路、１８……制
御スイツチ、１９……遅延回路、２１……メモリ
ー回路、２２……リセツトスイツチ、２３……表
示器。
The illustrated circuit is one embodiment of the counter device of the present invention. Explanation of main drawing numbers, 1... Battery, 2... Power switch, 5... Light emitting diode, 6 ... Photo coupler, 9... Photo transistor, 12... Switching transistor, 14 ... Pulse signal generation circuit , 15...Counter circuit, 18...Control switch, 19...Delay circuit, 21...Memory circuit, 22...Reset switch, 23...Display device.
Claims (1)
るパルス信号発生回路と、該パネル信号発生回路
からのパルス信号が入力されると共に再生及び早
送り動作時にはアツプカウントし、且つ巻戻し動
作時にはダウンカウントするカウンター回路と、
該カウンター回路のカウント動作に伴なうカウン
ト値を記憶すると共に常時電源が供給された状態
にあるメモリー回路と、前記カウンター回路のカ
ウント動作に伴なうカウント値を表示する表示器
と、テープレコーダが動作状態にあるとき閉成さ
れると共に前記パルス信号発生回路、カウンター
回路及び表示器へ電源を供給する電源スイツチと
該電源スイツチの閉成に伴なう電源供給時前記カ
ウンター回路のカウント動作の開始を所定時間遅
延せしめる遅延回路とより成るテープレコーダー
のカウンター装置。 A pulse signal generation circuit generates a panel signal as the reel shaft rotates, and the pulse signal from the panel signal generation circuit is input and counts up during playback and fast-forwarding operations, and counts down during rewinding operations. counter circuit,
A memory circuit that stores count values associated with the counting operation of the counter circuit and is constantly supplied with power, a display that displays the count values associated with the counting operation of the counter circuit, and a tape recorder. A power switch that is closed when the power switch is in operation and supplies power to the pulse signal generating circuit, the counter circuit, and the display, and a counting operation of the counter circuit when power is supplied as the power switch is closed. A tape recorder counter device comprising a delay circuit that delays the start by a predetermined period of time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17271484U JPH0325358Y2 (en) | 1984-11-14 | 1984-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17271484U JPH0325358Y2 (en) | 1984-11-14 | 1984-11-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6186888U true JPS6186888U (en) | 1986-06-06 |
| JPH0325358Y2 JPH0325358Y2 (en) | 1991-05-31 |
Family
ID=30730376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17271484U Expired JPH0325358Y2 (en) | 1984-11-14 | 1984-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325358Y2 (en) |
-
1984
- 1984-11-14 JP JP17271484U patent/JPH0325358Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0325358Y2 (en) | 1991-05-31 |
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