JPS6187322A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6187322A JPS6187322A JP59192301A JP19230184A JPS6187322A JP S6187322 A JPS6187322 A JP S6187322A JP 59192301 A JP59192301 A JP 59192301A JP 19230184 A JP19230184 A JP 19230184A JP S6187322 A JPS6187322 A JP S6187322A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- diffusion layer
- shallow
- mos
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
- H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
- H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置製造における、シリコン中べのＮ
型不純物拡散層の形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to the production of N in silicon in semiconductor device manufacturing.
The present invention relates to a method for forming a type impurity diffusion layer.
従来の半導体装置製造方法によるＮ型不純物拡散層の形
成は、Ｊ 、 Ｆ２１ｅｃｔｒｏｃｈｅｍ、Ｓｏｃ １
１４５、■０１ １５１．Ｎ（Ｌ５（１９８４）の様に
、３１ｐ＋イオンを、イオン注入装置を用いてシリコン
中に注入後１ハロジェン・ランプにより短時間アニーリ
ングを行なうことにより、浅い接合を持つ不純物拡散層
の形成がなされていた。Formation of an N-type impurity diffusion layer by a conventional semiconductor device manufacturing method is described in J, F21 electrochem, Soc 1
145,■01 151. As in N(L5 (1984)), an impurity diffusion layer with a shallow junction is formed by implanting 31p+ ions into silicon using an ion implanter and then annealing them for a short time using a halogen lamp. Ta.
しかし、前述の従来技術では、次の３個の問題点を有す
る。第１にイオン注入装置が高コスト力つ複雑な機能か
らなるため稼動率が悪い。このため拡！ｒ２ ／ｉ？ｊ
形成製造費が非常に高価にな、る。次に、シリコン中の
燐拡散層は接合が浅くなると、拡散抵抗が大きくなり、
０，２μｍ以下の接合深さを持つ燐鉱１ｎ層のシート抵
拍゛は、５０Ω／口より高コ■−抗となる。この高抵抗
は、例えば、ＭＯＳＦＥＴのソース・ドレインの拡Ｉ￥
１層においては、トランジスタのスイッチング・スピー
ドに制限を与えＬＳＩの高速化を防げる。最後に、シリ
コン中に３１ｐ＋ イオンを注入した場合、イオン注入
によるシリコンの欠陥は、３１Ｐの注入時の不純物分布
より５ｏｏｉＦ、５度深いため、短時間アニールを用い
ても、欠陥回復による増そく拡散が生じ、５００λ以下
の接合形成ができない。このため、イオン注入結晶欠陥
が、ＬＳＩの微細化に制限を与える従って、ＶＬＳＩの
製造において、従来の拡散層の形成方法は、ＶＬＳＩの
低コスト化、高速化、高集積化を困難にしていた。However, the above-mentioned conventional technology has the following three problems. First, the ion implantation device is expensive and has complicated functions, resulting in poor operating efficiency. Expand for this reason! r2/i? j
Forming manufacturing costs become very high. Next, the shallower the junction in the phosphorus diffusion layer in silicon, the greater the diffusion resistance.
The sheet resistance of a 1n layer of phosphate having a junction depth of 0.2 .mu.m or less is higher than 50 .OMEGA./hole. This high resistance is caused by, for example, the expansion of the source/drain I of a MOSFET.
In the first layer, it is possible to limit the switching speed of the transistor and prevent the LSI from increasing in speed. Finally, when 31p+ ions are implanted into silicon, defects in silicon due to ion implantation are 5ooiF, 5 degrees deeper than the impurity distribution during 31P implantation, so even if short-time annealing is used, the defect recovery will cause increased diffusion. occurs, making it impossible to form a bond of 500λ or less. For this reason, ion-implanted crystal defects limit the miniaturization of LSIs. Therefore, in the manufacture of VLSIs, conventional diffusion layer formation methods have made it difficult to reduce costs, increase speed, and increase integration of VLSIs. .
そこで、本発明は、このような問題点を解決するもので
、その目的とするところは、低いシート抵抗と浅い接合
を持つＮ型拡散層の製造が、安価に出来る方法を提供す
ることにある。特に、ＭＯＳＦＥＴからなるＶＬＳＩの
低コスト化、高速化、高集積化において有効である。Therefore, the present invention aims to solve these problems, and its purpose is to provide a method for manufacturing an N-type diffusion layer having low sheet resistance and shallow junctions at low cost. . In particular, it is effective in reducing costs, increasing speed, and increasing integration of VLSIs made of MOSFETs.
本発明の半導体装置の製造方法は、拡散層を形成すべき
領域に、Ｔｉ、Ｗ、Ｍｏ、Ｔａなどの高１勿；点金叫シ
リサイドを形成後、該シリサイド上に、スピン・コータ
ーにより燐を含むＳＯＧ （Ｓｐｉｎ−Ｏｎ−Ｇ’１ａ
ｓｓ ） 、以下Ｓ ＯＰ Ｓ Ｇ （５ｐｉｎ一旦ｎ
−Ｐｈｏｓｐｈｏｓｉｌｉｃａｔｅ−Ｉｑｌａｓｓ ）
と呼ぶ、を塗布し、５００℃以下の低温でベークした後
、ハロジェン・ランプにより９００℃以上の短時間熱処
理を行ない、該シリサイドが該拡￥ｉ層に覆われた拡散
層を形成することを特徴とする。In the method for manufacturing a semiconductor device of the present invention, after forming a high-density metal silicide such as Ti, W, Mo, Ta, etc. in a region where a diffusion layer is to be formed, phosphorus is coated on the silicide using a spin coater. SOG (Spin-On-G'1a
ss), hereinafter SOPSG (Once 5pin n
-Phosphosphosilicate-Iqlass)
After baking at a low temperature of 500°C or less, heat treatment is performed for a short time at 900°C or more using a halogen lamp to form a diffusion layer in which the silicide is covered with the expanded i-layer. Features.
本発明の作用を述べれば、シリコン基＆表面に蓄積され
た高融点金属シリサイドｎ＞ｋは、シート抵抗の低減に
寄与する。例えばＴ１シリサイドにおいては、５００″
Ａ程度の深さで約１０Ω／口のシー ） Ｊ’ｆｆ、ｔ
ｊＣを持つ。さらに、スピン・コーターによりＳ Ｏ’
Ｐ Ｓ Ｇを塗布し、ベーク後、ハロジェン・ランプを
用いて短時間熱処理する拡散層の製造方法は、スピン・
コルターとハロジェン・ランプ炉の安価で単純な装置を
用いるために、ＬＳＩの製造コストの低減に寄与する。To describe the effect of the present invention, the high melting point metal silicide n>k accumulated on the silicon base and surface contributes to a reduction in sheet resistance. For example, in T1 silicide, 500″
Approximately 10Ω/mouth sea at depth of A) J'ff, t
have jC. Furthermore, a spin coater is used to coat SO'
The method for manufacturing the diffusion layer is to apply PSG, bake it, and then heat it for a short time using a halogen lamp.
The use of inexpensive and simple equipment such as a coulter and a halogen lamp furnace contributes to reducing the manufacturing cost of LSI.
しかも、熱処理が単時間で行なわれるため、シリサイド
下に形成される燐拡散層は、５００λ以下の深さも可能
にし、戊い接合の形成に寄与する。燐の拡散係数は、シ
リコン中よりシリサイド中でのほうが数桁大きく、例え
ば、１０００℃６秒のハロジェン・ランプ熱処理におい
ては、１０００Ａ程度のシリサイド中を、５ＯＰＳＧ拡
散源から生じた燐が通過し、シリサイド下のシリコン基
４反中に約３００λ程度の貴拡散ハ１が形成される。Moreover, since the heat treatment is performed in a single hour, the phosphorus diffusion layer formed under the silicide can be formed to a depth of 500λ or less, contributing to the formation of an open junction. The diffusion coefficient of phosphorus is several orders of magnitude larger in silicide than in silicon. For example, in a halogen lamp heat treatment at 1000°C for 6 seconds, phosphorus generated from a 5OPSG diffusion source passes through silicide at about 1000A, A noble diffusion layer 1 of about 300λ is formed in the silicon base 4 under the silicide.
第１図は、本発明の実施例における、拡散層形成を行な
う半４体装（δ製造の断面図である。シリコン基板１上
に、シリサイド薄１１１．ｐ ２を形成し、５ＯＰＳＧ
５をスピン・コーターにより塗布後、ハロジェン・ラン
プ４を用いて短時間熱処理を行なっている。５は、シリ
コン基板への元の照射が均一になるように設計されたミ
ラーである。第４図散接合の断面図である。第１図に示
した熱処理（でより、５ＯＰＳＧ中の燐が、シリサイド
２下のシリコン基板領域７に拡散している。第２（２）
・第３図は、従来技術によりＮ型拡散層形成を行なう半
導体装置製造方法を示した断面図である。従来技術では
、シリコン基板１中に、イオン注入装置を用いて３ｉｐ
＋イオン６を注入（第２図）後、ハロジェン・ランプ４
により熱処理を行ない（第５図）、Ｎ型拡散接合７を形
成している。この時、イオン６を注入するためのイオン
注入装置は、高価で、装置が複雑なため稼働率も低い。FIG. 1 is a cross-sectional view of a half-packet (δ) fabrication for forming a diffusion layer in an embodiment of the present invention.A thin silicide layer 111.p2 is formed on a silicon substrate 1,
After applying 5 using a spin coater, a short heat treatment was performed using a halogen lamp 4. 5 is a mirror designed to make the original irradiation onto the silicon substrate uniform. FIG. 4 is a sectional view of a scattered joint. Due to the heat treatment shown in FIG. 1, phosphorus in 5OPSG is diffused into the silicon substrate region 7 under the silicide 2.
- FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device in which an N-type diffusion layer is formed using a conventional technique. In the conventional technology, an ion implanter is used to implant 3ips into the silicon substrate 1.
After implanting + ions 6 (Figure 2), the halogen lamp 4
A heat treatment is performed (FIG. 5) to form an N-type diffusion bond 7. At this time, the ion implantation device for implanting the ions 6 is expensive and complicated, so the operating rate is low.
このため従来の拡散層形成製造費が非常に高価である。For this reason, the manufacturing cost of conventional diffusion layer formation is very high.
さらＱζ、燐の固溶限界のため、Ｎ型拡散層の抵抗率が
’＋ｔｒ４Ｊ限され、接合が浅くなると、拡散抵抗が大
きくなる。また、イオン注入は、シリコン基板の結晶性
を破壊するため、イオン注入時の結晶欠陥は、燐不純物
分布より５００λ以上深く存在し、熱処理による欠陥回
復に伴う、燐不純物の増連拡散が生じ、５ｏｏＸ以下の
浅い接合形成ができない。以トの３貞Ａ；−ＶＬＳＩの
促Ｊ ａ ；ｆｔＭ Ｔ８ ｆ 六いて−Ｖ Ｔ。Furthermore, due to the solid solubility limit of Qζ and phosphorus, the resistivity of the N-type diffusion layer is limited to '+tr4J, and as the junction becomes shallower, the diffusion resistance increases. In addition, since ion implantation destroys the crystallinity of the silicon substrate, crystal defects at the time of ion implantation exist more than 500λ deeper than the phosphorus impurity distribution, and as the defects are recovered by heat treatment, increased diffusion of phosphorus impurities occurs. It is not possible to form a shallow junction of 5ooX or less. The following three cases A; - VLSI prompt J a; ftM T8 f six points - V T.
ＳＸの低コスト化、高速化、高集積化を防げる原因とな
る。一方、第１図、第４図に示した本発明による製造方
法では、イオン注入袋［ａに代わり５ＯＰＳＧを用い、
イオン注入法に代わり、高温短時間熱拡散法を用い、シ
ート抵抗の低減のためシリサイド薄膜層を形成している
ため、製造が安価ンこでき、シート抵抗の小さい浅い接
合が可能になる。１タリ造装置の低コスト化はＶＬＳＩ
を低コストにし、浅い接合はＶＬＳＩの微細化を可能に
し、低いシート抵抗で浅い接合はＶＬＳＩの高速化を可
能にする。This prevents the SX from becoming lower in cost, faster in speed, and more highly integrated. On the other hand, in the manufacturing method according to the present invention shown in FIGS. 1 and 4, 5OPSG is used instead of the ion implantation bag [a,
Instead of ion implantation, a high-temperature, short-time thermal diffusion method is used to form a silicide thin film layer to reduce sheet resistance, making manufacturing inexpensive and enabling shallow junctions with low sheet resistance. VLSI is the key to lowering the cost of single-task manufacturing equipment.
Shallow junctions enable miniaturization of VLSIs, and shallow junctions with low sheet resistance enable higher speeds of VLSIs.
第５図から第８図は、本発明によるＮ型拡散層の形成方
法をＭＯＳ −１１１ＩＥＴのソース・ドレイ／及びゲ
ートに適用した場合の工程断ｆｆｚｉ図である。5 to 8 are process cross-sectional views when the method for forming an N-type diffusion layer according to the present invention is applied to the source/drain/and gate of MOS-111IET.
第５図において、シリコン基板１上には、ゲート酸化膜
８．多結晶シリコンゲー）％極１０及びサイド・ワール
絶縁膜５１０２９が形成されている。Ｆ、 ６図におい
て、ゲート電極、ソース及びドレイン上に選択的に高融
点金属または高融点金属層１１を形成する。第７図では
、基板に５ＯＰＳＧ１２を各ピン・コーターにて塗布す
る。ベークし１ハロジェン・ランプによる高温短時間熱
処理を行なうことにより、第８図に示すような浅いＮ型
拡散層を持つＭＯ３−ＦＥＴが田来る。嬉意図のＭＯ３
−Ｆ’ＥＴでは、ソース・ドレイン領域において、シー
ト抵抗の小さいシリサイド１１が浅い燐拡散接合層１２
に覆われている。さらに、ゲート電極多結晶シリコン表
面層にもシリサイド層が形成されている。このため、浅
い接合は、接合容量を小さくし、ＭＯ３−１１１’Ｆｉ
Ｔのスイッチングを速くすると同時にＭＯＳ −ＦＩＴ
の微細化が可能になる。さらに、ソース・ドレイン及び
ゲー）を極のシリサイド層は各々のシート抵抗を小さく
しＭＯＳ −ＰＥＴのスイッチング速度に寄与する。In FIG. 5, a gate oxide film 8. A polycrystalline silicon (polycrystalline silicon) electrode 10 and a side swirl insulating film 51029 are formed. In FIG. 6, a high melting point metal or a high melting point metal layer 11 is selectively formed on the gate electrode, source and drain. In FIG. 7, 5OPSG12 is applied to the substrate using each pin coater. By baking and performing heat treatment at high temperature for a short time using a halogen lamp, an MO3-FET having a shallow N-type diffusion layer as shown in FIG. 8 is obtained. MO3 with happy intentions
- In the F'ET, in the source/drain region, the silicide layer 11 with low sheet resistance forms a shallow phosphorus diffusion bonding layer 12.
covered in. Furthermore, a silicide layer is also formed on the gate electrode polycrystalline silicon surface layer. Therefore, a shallow junction reduces the junction capacitance and MO3-111'Fi
MOS-FIT to speed up T switching and at the same time
miniaturization becomes possible. Furthermore, the silicide layers on the source, drain, and gate electrodes reduce their respective sheet resistances and contribute to the switching speed of the MOS-PET.
以上述べたように、本発明によれば、シリサイド表面上
に５ｏｐｓｏを形成し、ハロジェン・ランプ熱処理を行
なうことにより、安価にシート抵抗の低い浅いＮ型拡散
接合層を形成が可能になり、特に、ＭＯ９−ＦＥＴに適
用した場合、低コスト、高速度かつ高集積化されたＶＬ
ＳＩの製造方法を提供することができる。As described above, according to the present invention, by forming 5 opso on the silicide surface and performing halogen lamp heat treatment, it is possible to form a shallow N-type diffusion bonding layer with low sheet resistance at low cost. , low cost, high speed and highly integrated VL when applied to MO9-FET
A method for manufacturing SI can be provided.
第１図、第４図・・・・・・本発明によるＮ型拡散層形
成工程の断面図
第２図、＃Ｓ６図・・・・・・従来技術によるＮ型拡散
層形成工程断面図
第５文、第６図、第７図、第８図・・・・・・本発明に
よるＮ型拡散ｆ曽形成技術のＭＯＳＦＥＴへの適用工程
１’ｉ＃面図
１・・・・・・シリコ７Ｍ、１ｒｌ１
２・・・・・・シリサイド
６・・・・・・５ＯＰＳＧ
４・・・・・・ハロジェン・ランプ
５・・・・・・ミラー
６・・・・・・３１Ｆ＋ イオン
７・・・・・・燐拡散層
８・・・・−・ゲート酸化膜
９・・・・・・サイド・ワール５ｉｎ２１０・・・・・
・多結晶シリコン
１１・・・・・・シリサイド
１２・・・・・・燐拡散層
以 上Fig. 1, Fig. 4...... Cross-sectional view of the N-type diffusion layer forming process according to the present invention Fig. 2, #S6...... Cross-sectional view of the N-type diffusion layer forming process according to the prior art Sentence 5, Figure 6, Figure 7, Figure 8...Process of applying the N-type diffusion f so formation technology according to the present invention to MOSFET 1'i# side view 1... Silico 7M, 1rl1 2...Silicide 6...5OPSG 4...Halogen lamp 5...Mirror 6...31F+ Ion 7... ... Phosphorous diffusion layer 8 ... - Gate oxide film 9 ... Side swirl 5in210 ...
・Polycrystalline silicon 11...Silicide 12...Phosphorus diffusion layer or more
Claims (1)
を形成する半導体装置の製造において、該拡散層上には
１０００Å程度の薄膜高融点金属シリサイド層が形成さ
れ、該シリサイド層上には、スピン・コーターにより燐
不純物を含んだケイソ化合物を含む有機溶剤を塗布し、
５００℃以下の低温でベークした後、ハロジェン・ラン
プにより９００℃以上の短時間高温熱処理を行ない、該
シリサイド下の該単結晶シリコンまたは該多結晶シリコ
ン中に燐不純物拡散層を形成することを特徴とする半導
体装置の製造方法。In manufacturing a semiconductor device in which an N-type diffusion layer is formed in single-crystal silicon or polycrystalline silicon, a thin film high-melting point metal silicide layer of about 1000 Å is formed on the diffusion layer, and a spin-type metal silicide layer is formed on the silicide layer. An organic solvent containing a silica compound containing phosphorus impurities is applied using a coater,
After baking at a low temperature of 500°C or lower, a short-time high-temperature heat treatment of 900°C or higher is performed using a halogen lamp to form a phosphorus impurity diffusion layer in the single crystal silicon or polycrystalline silicon under the silicide. A method for manufacturing a semiconductor device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59192301A JPH0719759B2 (en) | 1984-09-13 | 1984-09-13 | Method for manufacturing semiconductor device |
| US06/756,895 US4669176A (en) | 1984-07-30 | 1985-07-19 | Method for diffusing a semiconductor substrate through a metal silicide layer by rapid heating |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59192301A JPH0719759B2 (en) | 1984-09-13 | 1984-09-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6187322A true JPS6187322A (en) | 1986-05-02 |
| JPH0719759B2 JPH0719759B2 (en) | 1995-03-06 |
Family
ID=16288995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59192301A Expired - Lifetime JPH0719759B2 (en) | 1984-07-30 | 1984-09-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719759B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308790A (en) * | 1992-10-16 | 1994-05-03 | Ncr Corporation | Selective sidewall diffusion process using doped SOG |
| US5312512A (en) * | 1992-10-23 | 1994-05-17 | Ncr Corporation | Global planarization using SOG and CMP |
| US5322805A (en) * | 1992-10-16 | 1994-06-21 | Ncr Corporation | Method for forming a bipolar emitter using doped SOG |
| US5340770A (en) * | 1992-10-23 | 1994-08-23 | Ncr Corporation | Method of making a shallow junction by using first and second SOG layers |
| US5340752A (en) * | 1992-10-23 | 1994-08-23 | Ncr Corporation | Method for forming a bipolar transistor using doped SOG |
| JPH07183505A (en) * | 1993-12-22 | 1995-07-21 | Nec Corp | Method for manufacturing semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55110036A (en) * | 1979-02-19 | 1980-08-25 | Fujitsu Ltd | Method for preparation of semiconductor device |
| JPS58168221A (en) * | 1982-03-29 | 1983-10-04 | Toshiba Corp | Preparation of semiconductor device |
| JPS58223320A (en) * | 1982-06-22 | 1983-12-24 | Ushio Inc | Diffusing method for impurity |
| JPS59105366A (en) * | 1982-12-08 | 1984-06-18 | Oki Electric Ind Co Ltd | Manufacturing method of MOS type transistor |
-
1984
- 1984-09-13 JP JP59192301A patent/JPH0719759B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55110036A (en) * | 1979-02-19 | 1980-08-25 | Fujitsu Ltd | Method for preparation of semiconductor device |
| JPS58168221A (en) * | 1982-03-29 | 1983-10-04 | Toshiba Corp | Preparation of semiconductor device |
| JPS58223320A (en) * | 1982-06-22 | 1983-12-24 | Ushio Inc | Diffusing method for impurity |
| JPS59105366A (en) * | 1982-12-08 | 1984-06-18 | Oki Electric Ind Co Ltd | Manufacturing method of MOS type transistor |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308790A (en) * | 1992-10-16 | 1994-05-03 | Ncr Corporation | Selective sidewall diffusion process using doped SOG |
| US5322805A (en) * | 1992-10-16 | 1994-06-21 | Ncr Corporation | Method for forming a bipolar emitter using doped SOG |
| US5312512A (en) * | 1992-10-23 | 1994-05-17 | Ncr Corporation | Global planarization using SOG and CMP |
| US5340770A (en) * | 1992-10-23 | 1994-08-23 | Ncr Corporation | Method of making a shallow junction by using first and second SOG layers |
| US5340752A (en) * | 1992-10-23 | 1994-08-23 | Ncr Corporation | Method for forming a bipolar transistor using doped SOG |
| US6010963A (en) * | 1992-10-23 | 2000-01-04 | Hyundai Electronics America | Global planarization using SOG and CMP |
| JPH07183505A (en) * | 1993-12-22 | 1995-07-21 | Nec Corp | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719759B2 (en) | 1995-03-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |