JPS6188560A - High withstanding-voltage schottky-barrier-diode - Google Patents

High withstanding-voltage schottky-barrier-diode

Info

Publication number
JPS6188560A
JPS6188560A JP59209207A JP20920784A JPS6188560A JP S6188560 A JPS6188560 A JP S6188560A JP 59209207 A JP59209207 A JP 59209207A JP 20920784 A JP20920784 A JP 20920784A JP S6188560 A JPS6188560 A JP S6188560A
Authority
JP
Japan
Prior art keywords
region
type
regions
layer
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59209207A
Other languages
Japanese (ja)
Other versions
JPH0370908B2 (en
Inventor
Kazuhisa Wada
和田 一久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP59209207A priority Critical patent/JPS6188560A/en
Publication of JPS6188560A publication Critical patent/JPS6188560A/en
Publication of JPH0370908B2 publication Critical patent/JPH0370908B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a diode having high reverse-blocking voltage by constituting a plurality of P type regions in dense equilateral hexagons when a P type annular region is formed to the surface layer section of an N type Si layer, the outside of the annular region is surrounded by an SiO2 film, the P type regions shaped into an N type layer surrounded by the annular region and these P type regions are coated with a Schottky barrier electrode. CONSTITUTION:An N type layer 12 is grown on an N<+> type Si substrate 11, on the back thereof a cathode electrode 17 is applied, a P type annular region 14 is diffused and shaped onto the surface layer section of the layer 12, and the outside of the region 14 is surrounded by an SiO2 film 15. A plurality of P type regions 13 are diffused and formed onto the surface layer section of the layer 12 surrounded by the region 14, and a Schottky barrier electrode 16 as an anode electrode is applied onto the surface containing these regions 13, but the regions 13 are shaped as follows at that time. That is, all of these regions 13 take an equilateral hexagon, spaced among these regions are made shorter than twice of the length of a space region extending when reverse voltage is applied, and projecting sections are formed previously at the apices of several triangle. Accordingly, a space charge region on an application in the opposite direction is extended over the whole surface of the layer 12, and reverse withstanding voltage is increased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はコノビューターなどの端末電子機器の工C化に
伴なう低電圧、大電流直流安定化電源において使用され
る整流用ダイオードに望まれる低い順電圧降下特性と比
較的高い逆阻止電圧特性を合わせもつダイオードに関す
るものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention is desirable for rectifying diodes used in low voltage, high current DC stabilized power supplies accompanying the conversion of terminal electronic devices such as conovulators to PC. This relates to a diode that has both low forward voltage drop characteristics and relatively high reverse blocking voltage characteristics.

〔従来技術〕[Prior art]

このようなダイオードの構造としてN形シリコン基板を
用いたショットキ・バリヤ・ダイオード(以降SBDと
略す)において、ショットキ・コンタクトの下側のシリ
コン基板表面にP形の不純物拡散領域を設け、ショット
キ・バリヤに基づく低い順電圧降下特性とPN接合に基
づく高い逆阻止電圧特性とを共に備える高耐圧SBDを
形成することは、例えば既にンリツド・ステート・エレ
クトロニクス(5olid 5tate 1ectro
nics ) 26(’83)P491〜493 の文
献により公知である。
In a Schottky barrier diode (hereinafter abbreviated as SBD) using an N-type silicon substrate as a diode structure, a P-type impurity diffusion region is provided on the silicon substrate surface below the Schottky contact, and the Schottky barrier Forming a high breakdown voltage SBD that has both low forward voltage drop characteristics based on PN junctions and high reverse blocking voltage characteristics based on PN junctions has already been developed, for example, in solid state electronics (5solid 5tate 1electro
nics) 26 ('83) P491-493.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述のような、いわば集積型とでもいうべきSBDは第
4図の要部断面図に示されるような構造を備えている。
The above-mentioned SBD, which can be called an integrated type, has a structure as shown in the cross-sectional view of the main part in FIG.

このSBDでは順方向電圧が、すなわちアノード  ″
電極3が正に、カソード電極4が負に、印加されると、
電流は主として堰層電圧の低いn領域1の表面8に接す
るショットキ・バリヤ領域5を流れ、堰層電圧の高いP
影領域2には流れない。逆方向電圧印加では電圧の増加
とともにPn’4合6のn領域l側に拡がり1点線で示
される空間電荷領域7aがn領域表面8を覆いつくし、
全体の降伏電圧はその外側のP形環状領域9による空間
電荷領域端7bでの降伏によって決まるようになる。
In this SBD, the forward voltage is
When the electrode 3 is applied positively and the cathode electrode 4 is applied negatively,
The current mainly flows through the Schottky barrier region 5 which is in contact with the surface 8 of the n region 1 where the weir layer voltage is low, and flows through the Schottky barrier region 5 which is in contact with the surface 8 of the n region 1 where the weir layer voltage is high.
It does not flow into shadow area 2. When a voltage is applied in the reverse direction, as the voltage increases, the space charge region 7a, which is shown by a single dotted line, spreads toward the n region l side of Pn' 4 and 6 and completely covers the n region surface 8.
The overall breakdown voltage is determined by the breakdown at the space charge region edge 7b due to the P-shaped annular region 9 outside.

このような集積型SBDは逆耐圧を重視すれば空間電荷
領域マaがn領域表面8を全て覆うようP影領域2をあ
る程度密に配列する必要がある。そうすると、順方向電
圧印加の際のSBD導通領域5の面積比率が小さくなる
ので堰層電圧が高くなり、低い順方向電圧降下特性をも
つというSBDの長所が損なわれる。反対に低い順電圧
降下特性を重視しすぎてP影領域2を疎にすると、逆電
圧印加時に空間電荷領域7aがn領域表面8を完全には
覆わなくなり、P影領域2を設けた意味がなくなる。
In such an integrated SBD, if emphasis is placed on the reverse breakdown voltage, it is necessary to arrange the P shadow regions 2 somewhat densely so that the space charge region ma covers the entire n region surface 8. In this case, the area ratio of the SBD conduction region 5 when applying a forward voltage becomes smaller, so that the weir layer voltage increases, and the advantage of the SBD of having a low forward voltage drop characteristic is lost. On the other hand, if too much emphasis is placed on low forward voltage drop characteristics and the P shadow region 2 is made sparse, the space charge region 7a will not completely cover the n region surface 8 when a reverse voltage is applied, and the purpose of providing the P shadow region 2 will be lost. It disappears.

従って本発明の目的は上記の欠点を改良し、できるだけ
j晒電圧降下が小さく、逆阻止電圧の高い高耐圧SBD
を提供することである。
Therefore, an object of the present invention is to improve the above-mentioned drawbacks and to develop a high-voltage SBD with as little exposure voltage drop and high reverse blocking voltage as possible.
The goal is to provide the following.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は前述の問題点を解決するためにP影領域の5、
形状と配列を工夫し、各P影領域のPni5合から、逆
方向印加された場合に拡がる空間電荷領域が互に重なる
ことなく、しかも所定の逆電圧印加のとき、n領域表面
8の全面を偉うような寸法関係のなかで、とくに著しい
効果をもつ寸法形状を見い出したことに基づくものであ
る。
In order to solve the above-mentioned problems, the present invention provides five points in the P shadow area.
By devising the shape and arrangement, the space charge regions that spread from the Pni5 of each P shadow region when applied in the opposite direction do not overlap each other, and moreover, when a predetermined reverse voltage is applied, the entire surface of the n region surface 8 is covered. This is based on the discovery of dimensions and shapes that have a particularly remarkable effect in the midst of significant dimensional relationships.

それは本発明によれば六角稠密(又は正三角稠密)状に
配置した正三角形の各頂点に中心をもつ正六角形であっ
て、かつそれぞれの正六角形の各頂点に突起を備える形
状のP影領域がショットキ・バリヤ領域下に配置されて
いることにより得られる。
According to the present invention, the P shadow region is a regular hexagon having a center at each vertex of an equilateral triangle arranged in a hexagonal dense (or equilateral triangular dense) manner, and has a protrusion at each vertex of each regular hexagon. is obtained by disposing the area under the Schottky barrier region.

〔作用および実施例〕[Function and Examples]

以下本発明の一実施例について図面を用いて詳細に説明
する。
An embodiment of the present invention will be described in detail below with reference to the drawings.

第1図波歪第3図は本発明の高耐圧ショットキ・バリヤ
・ダ°イオードを示す図である。これらの図において、
同符号は同一の部分を示す。
FIG. 1 shows wave distortion. FIG. 3 shows a high breakdown voltage Schottky barrier diode of the present invention. In these figures,
The same symbols indicate the same parts.

第1図は本発明による高耐圧SBDであって、そのアノ
ード電極であるショットキ・バリヤ電極16を上から透
して見た上面図である。ショットキ・バリヤ電極16の
下のn形シリコン基板の表面に設けられたP彫工六角形
状領域13がショットキ・バリヤ電極とシリコンと接す
るショットキ・バリヤ領域内において、相互に逆電圧印
加時に延びる空間電荷領域の長さの2倍より少し短かい
距離で、しかも後で述べるような所定の配置に従って均
一に分布しており、さらにショットキ・バリヤ領域の外
側境界にはP形の環状領域14が設けられている。その
外側の領域15はシリコン酸化膜のような表面保腹膜の
領域である。P彫工六角形領域13とP形環状領域14
との間隔は、正六角形領域13の形状を必要以上に複雑
なものにしないため、前記の空間電荷領域の長さの2倍
以内という範囲で、前記正六角形領域13の相互間の間
隔と異ならせることができる。このようにすることによ
り逆電圧が印加されたときに空間電荷領域がショットキ
・バリヤ領域全体を覆うようになり、逆阻止電圧はP形
環状領域の外側に延びる空間電荷領域端での降伏によっ
て決まることになる。
FIG. 1 is a top view of a high voltage SBD according to the present invention, looking through a Schottky barrier electrode 16, which is an anode electrode thereof. In the Schottky barrier region where the P-carved hexagonal region 13 provided on the surface of the n-type silicon substrate under the Schottky barrier electrode 16 contacts the Schottky barrier electrode and silicon, a space charge region extends when reverse voltages are applied to each other. are uniformly distributed at a distance of slightly less than twice the length and according to a predetermined arrangement as will be described later, and furthermore, a P-shaped annular region 14 is provided at the outer boundary of the Schottky barrier region. There is. The outer region 15 is a region of a surface peritoneal membrane such as a silicon oxide film. P carved hexagonal area 13 and P-shaped annular area 14
In order not to make the shape of the regular hexagonal regions 13 more complicated than necessary, the distance between the regular hexagonal regions 13 should be different from the distance between the regular hexagonal regions 13 within twice the length of the space charge region. can be set. This allows the space charge region to cover the entire Schottky barrier region when a reverse voltage is applied, and the reverse blocking voltage is determined by the breakdown at the edge of the space charge region extending outside the P-shaped annular region. It turns out.

次にP彫工六角形領域の形状と配置についてさらに詳し
く述べる。第2図は第1図に示される高耐圧ショットキ
・バリヤ・ダイオードの断面図で、ある。符号16はア
ノードとなるショットキ・ノくリヤ電極であり、符号1
7はカソード電極である。第2図においてシリコンのn
形低抵抗率基板11に積層されたn形高抵抗率シリコン
層12の抵抗率ρによって定まるPn接合のアバランシ
ェ降伏電圧もしくはツェナ降伏電圧をVzとすると、逆
電圧印加時にP彫工六角形領域13のところのPn接合
から拡がる空間電荷領域距離L(ミクロン)はL = 
0.53 r「7−−と近似されることが知られている
。従って、本発明の目的に適うP彫工六角形領域13相
互の距離を2Lとすると、L≦0.5367Wであるが
実際lては安全率を0.95と見込み、これを乗じてL
−o、:a(fiiとすることができるし、またこの方
が望ましい。
Next, the shape and arrangement of the P carving hexagonal area will be described in more detail. FIG. 2 is a cross-sectional view of the high voltage Schottky barrier diode shown in FIG. 1. Reference numeral 16 is a Schottky rear electrode serving as an anode, and reference numeral 1
7 is a cathode electrode. In Figure 2, n of silicon
Let Vz be the avalanche breakdown voltage or Zener breakdown voltage of the Pn junction determined by the resistivity ρ of the n-type high-resistivity silicon layer 12 laminated on the low-resistivity substrate 11. However, the space charge region distance L (microns) extending from the Pn junction is L =
It is known that it is approximated as 0.53 r'7. Therefore, if the distance between the P carving hexagonal areas 13 suitable for the purpose of the present invention is 2L, L≦0.5367W, but in reality The safety factor is expected to be 0.95, and multiplied by this, L
-o, :a(fii), and this is preferable.

このP彫工六角形領域13の上面形状は第3図の拡大図
に示すように正六角形13bであって、しかも第1図に
示すように正三角形を相互に稠密に敷きつめて得られる
六角稠密(又は正三角稠密)に配列された正三角形にの
各頂点に+ lK2 +Ksにそれぞれ中心をもつよう
に配置されているので、シリコン表面での空間電荷領域
の相互の重なりを第3図の黒芯で示すように最も少なく
することができる。
The upper surface shape of this P carved hexagonal area 13 is a regular hexagon 13b as shown in the enlarged view of FIG. 3, and moreover, as shown in FIG. The overlap of the space charge regions on the silicon surface can be expressed as the black center in Figure 3. can be minimized as shown in .

P彫工六角形領域13bの大きさく外接円の半径をdと
する)はできるだけ小さいことが望ましい、例えば、半
専体素子の製造に−一けるホト工程できまる寸法精度か
らは3〜5ミクロンとするのが最適である。
It is desirable that the size of the P carved hexagonal region 13b (where d is the radius of the circumscribed circle) is as small as possible. For example, from the dimensional accuracy achieved in the photo process required for manufacturing semi-dedicated elements, it is 3 to 5 microns. It is best to do so.

正六角形領域の相互中心距離をD(ミクロン)す、シリ
コンの抵抗率ρと降伏電圧Vzが決まればDが求まるこ
とになる。ところで、このように最大空間電荷領域の重
なりを少なくなるように配置すると、正六角形P影領域
の最大空間電荷領域端の上面形状は第3図の点線で示さ
れるものとなるが、この第6図のように3本の点綴の交
点E付近では重ならない場所が生じることが判明した。
If the mutual center distance of the regular hexagonal regions is D (microns), and the resistivity ρ and breakdown voltage Vz of silicon are determined, D can be found. By the way, if the maximum space charge regions are arranged so that the overlap of the maximum space charge regions is reduced in this way, the upper surface shape of the maximum space charge region end of the regular hexagonal P shadow region will be as shown by the dotted line in FIG. As shown in the figure, it has been found that there are areas where the three dots do not overlap near the intersection E.

これを本発明の目的に適うようにしてなお防止するには
それぞれの正六角形領域13aの各角部Alこ外方Bに
向う長さtの突起ABを付加するとよいことが確かめら
れた。この突起ABは正六角形領域i3aのみならずシ
ョットキ・バリヤ領域下に設けられた最外周を除くすべ
ての正六角形領域の角SVて形成式れねばならないこと
は言うまでもない。
It has been found that in order to prevent this problem while still meeting the purpose of the present invention, it is effective to add a protrusion AB having a length t facing outward B to each corner Al of each regular hexagonal area 13a. It goes without saying that this projection AB must be formed not only at the regular hexagonal region i3a but also at the corner SV of all the regular hexagonal regions except the outermost periphery provided under the Schottky barrier region.

この突起ABは正六角形の角部Aから突起の先g!jB
までの長さをtとすると、 となる。実際にはtキ0.16 Lが好ましい。突起の
幅はできるだけ小さくてよく、例えば1ミクロンを選択
することができる。
This protrusion AB is from the corner A of the regular hexagon to the tip g! jB
Letting the length up to t be t, it becomes. Actually, 0.16 L is preferable. The width of the protrusion may be as small as possible, for example 1 micron can be selected.

このようにして定めた突起形状が第3図の正六角形領域
13aに示されている。
The protrusion shape determined in this way is shown in the regular hexagonal area 13a in FIG.

この形状によるP彫工六角形領域を備えるSBDは逆電
圧印加時にはSBD部のすべての領域が空間電荷領域で
覆われることになる。従ってPn接合して基づく高い逆
阻止電圧が得られる。またこのP影領域13aの配列を
六角稠密状にしきつめた正三角形の角頂点に01の中心
がくるように配置されているため、空間電荷領域の最大
波がり時における相互の重なりをほとんど無しにするこ
とができ、その結果所定の逆電圧に対して正六角形領域
の全面積を最も小さくなるので、順方向電圧印加のとき
の堰層電圧もまた最少となる。
In an SBD having a P-carved hexagonal region having this shape, the entire region of the SBD portion is covered with a space charge region when a reverse voltage is applied. Therefore, a high reverse blocking voltage based on the Pn junction can be obtained. In addition, since the P shadow regions 13a are arranged so that the center of 01 is at the corner apex of an equilateral triangle that is tightly arranged in a hexagonal dense manner, there is almost no mutual overlap when the space charge regions are at their maximum wave. As a result, the total area of the regular hexagonal region is minimized for a given reverse voltage, so that the weir layer voltage when a forward voltage is applied is also minimized.

〔発明の効果〕〔Effect of the invention〕

本発明によればショットキ・バリヤ・ダイオードにおい
てバリヤ領域内に配設される不純物拡散領域の形状が六
角稠密配列された正三角形の各頂点にそれぞれ中心をも
つ正六角形であって、かつそれぞれの正六角形の各頂点
に降伏電圧印加時の空間電荷領域がショットキ・バリヤ
領域を残りくまなく覆うような突起を備えるようにした
ので順電圧降下が小嘔く、逆阻止電圧の高いショットキ
・バリヤ・ダイオードを得ることができる。
According to the present invention, in a Schottky barrier diode, the shape of the impurity diffusion region disposed in the barrier region is a regular hexagon having a center at each vertex of an equilateral triangle arranged in a close-packed hexagonal arrangement, and A Schottky barrier diode with a small forward voltage drop and high reverse blocking voltage because each vertex of the square has a protrusion so that the space charge region completely covers the Schottky barrier region when a breakdown voltage is applied. can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す上面図、第2図は同上
の断面図、第3図は同上の正六角形領域の拡大図、第4
図は従来の集積型7ヨツトキ・バリヤ・ダイオードの要
部断面図である。 13・・・正六角形領域、14・・・環状領域、16・
ショットキ・バリヤ電極、17・・・カソード電極、A
B・・突辺。
FIG. 1 is a top view showing one embodiment of the present invention, FIG. 2 is a sectional view of the same, FIG. 3 is an enlarged view of the regular hexagonal area of the same, and FIG.
The figure is a sectional view of essential parts of a conventional integrated seven-layer barrier diode. 13... Regular hexagonal area, 14... Annular area, 16.
Schottky barrier electrode, 17... cathode electrode, A
B...Protrusion.

Claims (1)

【特許請求の範囲】[Claims]  ショットキ・バリヤ領域下の半導体表面に該半導体と
は異なる導電型の複数個の不純物拡散領域が設けられ、
それぞれの領域の相互間隔が降伏電圧印加時におけるP
n接合の外側に拡がる空間電荷領域の長さの2倍より短
かくなるように配置されてなるものにおいて、前記不純
物拡散領域の形状が、相互に稠密に敷きつめられた正三
角形の各頂点にそれぞれ中心をもつ正六角形であつて、
かつそれぞれの正六角形の各頂点には降伏電圧印加時の
空間電荷領域がショットキ・バリヤ領域を残りくまなく
覆うような突起を備えていることを特徴とする高耐圧シ
ョットキ・バリヤ・ダイオード。
A plurality of impurity diffusion regions of a conductivity type different from that of the semiconductor are provided on the semiconductor surface under the Schottky barrier region,
The distance between each region is P when the breakdown voltage is applied.
In the case where the length of the space charge region extending outside the n-junction is shorter than twice, the shape of the impurity diffusion region is at each vertex of an equilateral triangle that is densely laid out. It is a regular hexagon with a center,
A high-voltage Schottky barrier diode characterized in that each vertex of each regular hexagon has a protrusion such that a space charge region completely covers the Schottky barrier region when a breakdown voltage is applied.
JP59209207A 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode Granted JPS6188560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59209207A JPS6188560A (en) 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59209207A JPS6188560A (en) 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode

Publications (2)

Publication Number Publication Date
JPS6188560A true JPS6188560A (en) 1986-05-06
JPH0370908B2 JPH0370908B2 (en) 1991-11-11

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JP59209207A Granted JPS6188560A (en) 1984-10-05 1984-10-05 High withstanding-voltage schottky-barrier-diode

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Country Link
JP (1) JPS6188560A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105465A (en) * 1988-10-14 1990-04-18 Sanken Electric Co Ltd Schottky barrier semiconductor device
JPH03105975A (en) * 1989-09-20 1991-05-02 Hitachi Ltd Semiconductor rectifier diode; power-supply apparatus and computer using it
US5278443A (en) * 1990-02-28 1994-01-11 Hitachi, Ltd. Composite semiconductor device with Schottky and pn junctions
CN103545382A (en) * 2013-11-12 2014-01-29 株洲南车时代电气股份有限公司 A junction barrier Schottky diode and its manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02105465A (en) * 1988-10-14 1990-04-18 Sanken Electric Co Ltd Schottky barrier semiconductor device
JPH03105975A (en) * 1989-09-20 1991-05-02 Hitachi Ltd Semiconductor rectifier diode; power-supply apparatus and computer using it
US5278443A (en) * 1990-02-28 1994-01-11 Hitachi, Ltd. Composite semiconductor device with Schottky and pn junctions
CN103545382A (en) * 2013-11-12 2014-01-29 株洲南车时代电气股份有限公司 A junction barrier Schottky diode and its manufacturing method

Also Published As

Publication number Publication date
JPH0370908B2 (en) 1991-11-11

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