JPS618951A - Wiring formation method - Google Patents

Wiring formation method

Info

Publication number
JPS618951A
JPS618951A JP59130403A JP13040384A JPS618951A JP S618951 A JPS618951 A JP S618951A JP 59130403 A JP59130403 A JP 59130403A JP 13040384 A JP13040384 A JP 13040384A JP S618951 A JPS618951 A JP S618951A
Authority
JP
Japan
Prior art keywords
wiring
deposited
resist pattern
metal
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59130403A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sano
佐野 芳明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59130403A priority Critical patent/JPS618951A/en
Publication of JPS618951A publication Critical patent/JPS618951A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the reliability of wiring, by using a common resist pattern, alternately depositing the insulating film of the first deposited film and the wiring metal of the second deposited film, performing only one lift OFF, thereby forming the wiring very simply. CONSTITUTION:A resist pattern 2 is formed on a ground layer 1, which is a substrate. The resist pattern 2 has a hole 3 corresponding to a wiring pattern in an area, where wiring is formed. On the upper side of the resist pattern 2 including the hole 3, the first deposited film, e.g., an insulating film 4, is deposited by a depositing method with less directivity. Then the second deposited film, e.g., a wiring metal, is deposited by a depositing method with high directivity. At this time, the wiring metal 5 is deposited in the vertical direction with respect to the surface of the substrate by an electron beam evaporating method as shown by wiring metal parts 5a and 5b on the insulating layer parts 4a and 4b, respectively, for example platinum is evaporated. When the resist pattern 2 is dissolved and the lift OFF is performed, the wiring metal part 5b on the insulating film 4b is formed as the metal wiring.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体装置が有する配線の形成方法に関する
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming wiring included in a semiconductor device.

(従来の技術) 従来の半導体装置の配線構造のうち二層配線構造のもの
がある。その場合、配線相互間で絶縁分離を行う必要が
ある。これがため、この二層配線構造を形成するに当り
、第一配線を形成した後、CVD法によってウェハ全面
上に絶縁膜を被着させ、然る後、この絶縁膜上にレジス
トパターンを形成し、続いて、第二配線用の金属層を被
着させ、最後にリフトオフ法により、レジストパターン
を溶解除去して第二配線を形成していた。
(Prior Art) Among the wiring structures of conventional semiconductor devices, there is a two-layer wiring structure. In that case, it is necessary to insulate and separate the wiring lines from each other. Therefore, in forming this two-layer wiring structure, after forming the first wiring, an insulating film is deposited on the entire surface of the wafer by CVD, and then a resist pattern is formed on this insulating film. Then, a metal layer for the second wiring is deposited, and finally the resist pattern is dissolved and removed by a lift-off method to form the second wiring.

(発明が解決しようとする問題点) このように、従来方法では、先に形成した電極配線を絶
縁膜で保護する場合には、先に形成した金属配線、例え
ば第−配線又は第二配線、を有するウニ八全面上に、再
度、CVD法で絶縁膜を被着させる工程が必要となり、
さらに、不必要な領域にも絶縁膜が被着してしまうため
、これを取り除くための新たなエツチング工程が必要で
あった。
(Problems to be Solved by the Invention) As described above, in the conventional method, when protecting the previously formed electrode wiring with an insulating film, the previously formed metal wiring, for example, the first wiring or the second wiring, It is necessary to apply an insulating film again using the CVD method on the entire surface of the sea urchin, which has
Furthermore, since the insulating film adheres to unnecessary areas, a new etching process is required to remove it.

この発明の第一の目的は一回のリフトオフ工程によって
配線直下の必要とする部分にのみ絶縁膜を簡単に形成出
来る配線形成方法を提供することにある。
The first object of the present invention is to provide a wiring forming method that can easily form an insulating film only in the necessary portion directly under the wiring by a single lift-off process.

この発明の第二の目的は一回のリフトオフ工程によって
絶縁膜で保護された配線を簡単に得る配線形成方法を提
供することにある。
A second object of the present invention is to provide a wiring forming method that easily obtains wiring protected by an insulating film through a single lift-off process.

(問題点を解決するための手段) この目的の達成を図るため、この発明においては、穴の
口部の幅が底部の幅より狭い断面形状を持った当該穴を
有するレジストパターンを下地層、    1°:**
t6I!1.!−,、:峠H°′加“パ′−ンの上側に
、指向性の少ない被着方法で、 @ −被着膜を被着す
る工程と、指向性の強い被着方法で第二被着膜を被着す
る工程と、前述のレジストパターンを溶解して除去して
配線を形成するリフトオフ工程とを含むことを特徴とす
る。
(Means for Solving the Problems) In order to achieve this object, in the present invention, a resist pattern having a cross-sectional shape in which the width of the opening of the hole is narrower than the width of the bottom is used as a base layer. 1°: **
t6I! 1. ! -,,: A step of applying a @-adhesive film on the upper side of the pass H°'addition pattern using a less directional deposition method, and a second coating using a highly directional deposition method. It is characterized by including a step of depositing a deposited film, and a lift-off step of dissolving and removing the resist pattern described above to form wiring.

(作用) このような方法によれば、共通のレジストパターンを用
い、第一被着膜の絶縁層と第二被着膜の配線金属を交互
に順次に被着した後に、−回のりフトオフを行うだけで
あるので、従来方法よりも非常に簡単に配線を形成する
ことが出来る。
(Function) According to such a method, after the insulating layer of the first deposited film and the wiring metal of the second deposited film are alternately and sequentially deposited using a common resist pattern, the -turn lift-off is performed. Since it is only necessary to perform the following steps, the wiring can be formed much more easily than the conventional method.

レジストパターンの穴の寸法、指向性の弱い被着方法及
び指向性の強い被着方法によって規制された寸法の配線
及び絶縁層を形成出来るので、従来よりも配線の信頼性
を著しく高めることが出来る。
Wiring and insulating layers can be formed with dimensions regulated by the hole dimensions of the resist pattern, weakly directional deposition methods, and strong directional deposition methods, making it possible to significantly improve the reliability of the wiring compared to conventional methods. .

(実施例) 以下1図面を参照してこの発明の詳細な説明する。(Example) The present invention will be described in detail below with reference to one drawing.

1=JJJ                  。1 = JJJ.

第1図(1)〜(It)は。。発明。第一実施例を説 
     1f明するための路線的断面図で、穴の部分
は横断面を示している。
FIG. 1 (1) to (It) are. . invention. The first example will be explained.
1f is a cross-sectional view for clarity, and the hole portion shows a cross section.

先ず、下地層l上に通常の方法でレジストパターン2を
、例えばtp■程度の厚さで、形成する。この場合、下
地層1を例えば基板とする。このレジストパターン2は
、配線が形成される予定領域にその配線パターンに対応
したパターンの穴3を有している。この穴3は、その口
部の幅W1が底部の輻W2より狭くなっていて、例えば
、逆テーパ状の断面形状となっている。
First, a resist pattern 2 is formed on the base layer 1 by a conventional method to a thickness of, for example, about tp. In this case, the base layer 1 is, for example, a substrate. This resist pattern 2 has holes 3 in a pattern corresponding to the wiring pattern in an area where wiring is to be formed. This hole 3 has a width W1 at its mouth narrower than a width W2 at its bottom, and has, for example, a reverse tapered cross-sectional shape.

次に、第1図(B)に示すように、この穴3を含むレジ
ストパターン2の上側に、指向性の少ない被着方法で、
第一被着膜、例えば、絶縁膜4を被着する。この絶縁膜
4はレジストパターン4の表面上に付着する(この絶縁
層部分を4aで示す)と共に、六3の底部である基板l
の全面にもある程度一様に付着する(この絶縁層部分を
4bで示す)。この場合、絶縁膜4を、スパッタ法によ
って例えば1000〜5000A程度の厚さのシリコン
酸化膜を堆積させることによって、形成する。
Next, as shown in FIG. 1(B), the upper side of the resist pattern 2 including the holes 3 is coated with a less directional coating method.
A first deposited film, for example an insulating film 4, is deposited. This insulating film 4 is attached to the surface of the resist pattern 4 (this insulating layer portion is shown as 4a), and the substrate l which is the bottom of the 63
(this insulating layer portion is shown as 4b). In this case, the insulating film 4 is formed by depositing a silicon oxide film having a thickness of, for example, about 1000 to 5000 Å using a sputtering method.

次に、第1図(C)に示すように、指向性の強い被着方
法で第二被着膜、例えば、配線金属を被着する。この場
合、電子ビーム蒸着法で基板面に垂直な方向から配線金
属5として、例えば、白金を蒸着することにより、絶縁
層部分4a及び4b上にそれぞれ配線金属部分5a及び
5bで示すように堆積する。この白金は、電子ビームの
強い指向性のため、絶縁層4aの、穴3の口部に対応す
る端縁によって制限されて、絶縁層4b上に配線金属5
bとして堆積されるが、レジストパターン2の中央部、
従って、絶縁層4b上にこの穴3のほぼ中央部において
堆積し、この穴の壁には付着することがない。
Next, as shown in FIG. 1C, a second deposited film, for example, a wiring metal, is deposited using a highly directional deposition method. In this case, for example, platinum is deposited as the wiring metal 5 from a direction perpendicular to the substrate surface using an electron beam evaporation method, thereby depositing the wiring metal parts 5a and 5b on the insulating layer parts 4a and 4b, respectively. . Due to the strong directivity of the electron beam, this platinum is limited by the edge of the insulating layer 4a corresponding to the mouth of the hole 3, and is applied to the wiring metal 5 on the insulating layer 4b.
b, but the central part of resist pattern 2,
Therefore, it is deposited on the insulating layer 4b at approximately the center of the hole 3, and does not adhere to the walls of the hole.

次に、第1図(It)に示すように、レジストパターン
2を溶解してリフトオフを行うと、絶縁膜4b上の配線
金属部分5bが金属配線として形成されるので、絶41
b上にセルファライン的に位置した金属配線が得られる
Next, as shown in FIG. 1(It), when the resist pattern 2 is dissolved and lift-off is performed, the wiring metal portion 5b on the insulating film 4b is formed as a metal wiring, so that the resist pattern 2 is completely removed.
Metal wiring located in a self-aligned manner on b is obtained.

1;1差1 次に、第2図(A)〜(Il)を参照してこの発明の第
二実施例につき説明する。尚、これら図において、第1
図に示した構成成分と同じ構成成分にっいては同一の番
号を付して示す、又、第一実施例と第二実施例と相違す
る点は、絶縁層と配線金属の形成順序が入れ替わってい
る点であり、その他の点は同一であるので、その詳細な
説明を省略する。
1; 1 difference 1 Next, a second embodiment of the present invention will be described with reference to FIGS. 2(A) to (Il). In addition, in these figures, the first
Components that are the same as those shown in the figures are indicated by the same numbers, and the difference between the first and second embodiments is that the order of formation of the insulating layer and the wiring metal is reversed. Since the other points are the same, detailed explanation thereof will be omitted.

第2図(A)に示すように、下地層1としての基板上に
第一実施例の場合と同様な穴3を有するレジストパター
ン2を形成した後、先ず、指向性の強い被着方法、例え
ば電子ビーム蒸着法、によって配線金属5 (5a、 
5b)として白金を基板1の基板面に垂直な方向から蒸
着する。
As shown in FIG. 2(A), after forming a resist pattern 2 having holes 3 similar to those in the first embodiment on a substrate as a base layer 1, first, a highly directional deposition method is applied. For example, the wiring metal 5 (5a,
As step 5b), platinum is deposited on the substrate 1 from a direction perpendicular to the substrate surface.

この時、電子ビーム蒸着法の強い指向性及びレジストパ
ターン2の逆テーパ状の形状のため、第2図(B)に示
すように、この配線金属5は六3の壁部分に付着するこ
となく、レジストパターン2の表面部分に配線金属部分
5aとして堆積すると共に、穴3内の基板lの表面に配
線金属部分5bとしI      て堆積する。
At this time, due to the strong directivity of the electron beam evaporation method and the reverse tapered shape of the resist pattern 2, the wiring metal 5 does not adhere to the wall portion of the 63, as shown in FIG. 2(B). , is deposited on the surface of the resist pattern 2 as a wiring metal portion 5a, and is also deposited on the surface of the substrate l in the hole 3 as a wiring metal portion 5b.

次に、第2図(C)に示すように、指向性の少ない被着
方法1例えばスパッタ法、により絶縁膜4としてシリコ
ン酸化膜を付着すると、指向性が弱いので、このシリコ
ン酸化膜はレジストパターン2の穴3内においても4b
で示すような絶縁層部分として一様に堆積すると共に、
穴3外の配線金属部分5a上にも4aで示すような絶縁
層部分として堆積する。
Next, as shown in FIG. 2(C), when a silicon oxide film is deposited as an insulating film 4 by a deposition method 1 with low directivity, such as sputtering, the silicon oxide film has weak directivity, so this silicon oxide film can be used as a resist. 4b also in hole 3 of pattern 2
It is deposited uniformly as an insulating layer part as shown in
An insulating layer portion as shown by 4a is also deposited on the wiring metal portion 5a outside the hole 3.

続いて、レジストパターン2の溶解によりリフトオフを
行うと、第2図(D)に示すような配線金属部分5bか
ら成る金属配線が形成されるので、セルファライン的に
絶縁膜で保護された金属配線が得られる。
Subsequently, when lift-off is performed by dissolving the resist pattern 2, a metal wiring consisting of the wiring metal portion 5b as shown in FIG. is obtained.

上述した各実施例では、穴3の断面構造を逆テーパ状と
したが、この穴の断面形状を、例えばシリコン酸化膜の
ような絶縁膜をその上側に被着したレジストパターンの
穴を介してアンダーエッチソゲして得られた二層構造に
よる逆台形の形状とすることもできる。その場合にも、
穴の口部の幅が穴の底部の幅よりも狭いので、前述した
実施例      t:1 の場合と同様にセルファライン的に金属配線を形成する
ことが出来る。
In each of the above-described embodiments, the cross-sectional structure of the hole 3 is inversely tapered, but the cross-sectional shape of the hole 3 can be changed, for example, through a hole in a resist pattern on which an insulating film such as a silicon oxide film is deposited. It is also possible to have an inverted trapezoidal shape with a two-layer structure obtained by under-etching. In that case too,
Since the width of the opening of the hole is narrower than the width of the bottom of the hole, metal wiring can be formed in a self-aligned manner as in the case of Example t:1 described above.

さらに、同一のレジストパターンを使用して絶縁層と配
線金属とを交互に積層させることにより、多層配線構造
を一回のリフトオフ工程で形成することが出来る。
Furthermore, by alternately stacking insulating layers and wiring metals using the same resist pattern, a multilayer wiring structure can be formed in a single lift-off process.

(発明の効果) 上述した説明からも明らかなように、この発明の方法に
おいて、レジストパターンの穴の口部が底部よりも幅狭
の当該穴を通じて指向性の少ない被着法を用いて第一被
着膜の絶縁層を堆積させた後に、指向性の強い被着法を
用いて第二被着膜の配線金属を堆積させる場合には、共
通のレジストパターンを用いた一回のリフトオフ工程で
、絶縁膜上に適度の余裕、すなわち、絶縁膜の幅よりも
少し狭い幅の金属配線を簡単に形成することが出来る。
(Effects of the Invention) As is clear from the above description, in the method of the present invention, the mouth of the hole in the resist pattern is formed through the hole, which is narrower than the bottom, using a less directional deposition method. After depositing the insulating layer of the deposited film, if a highly directional deposition method is used to deposit the wiring metal of the second deposited film, it is possible to deposit the wiring metal of the second deposited film in a single lift-off process using a common resist pattern. , it is possible to easily form a metal wiring on the insulating film with an appropriate margin, that is, with a width slightly narrower than the width of the insulating film.

従って、この発明によれば、他の配線との交差配線を著
しく簡単な工程で行うことが出来、例えば、多くの配線
の絶縁された交差を必要とするICとかLSIとかの製
造に利用することが出来る。
Therefore, according to the present invention, cross wiring with other wiring can be performed in an extremely simple process, and can be used, for example, in manufacturing ICs and LSIs that require insulated crossing of many wirings. I can do it.

又、この発明の方法において、指向性の強い被着法であ
る電子ビーム蒸着法による配線金属の蒸着後に指向性の
弱い被着法であるスパッタ法により絶縁層の付着を行っ
てリフトオフを行うと、配線金属がセルファライン的に
レジストパターンの穴の底部の幅で規定される幅を有す
る絶縁膜によって被覆された構造の配線を得ることが出
来るので、従来の方法よりも配線の信頼性が著しく向上
する。又、この発明の方法では、他の配線を絶縁して交
差させる時には、新たに絶縁膜の付着工程を必要としな
いので、交差配線工程を短縮出来るという利点がある。
In addition, in the method of the present invention, after the wiring metal is deposited by electron beam evaporation, which is a highly directional deposition method, an insulating layer is deposited by sputtering, which is a weakly directional deposition method, and lift-off is performed. Since it is possible to obtain a wiring structure in which the wiring metal is covered with an insulating film having a width defined by the width of the bottom of the hole in the resist pattern in a self-aligned manner, the reliability of the wiring is significantly higher than that of conventional methods. improves. Furthermore, the method of the present invention does not require a new step of attaching an insulating film when insulating and intersecting other wirings, so there is an advantage that the cross-wiring process can be shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)〜(D)及び第2図(A)〜(D)はそれ
ぞれこの発明の詳細な説明するための工程図である。 l・・・下地層、     2・・・レジストパターン
3・・・穴、       4・・・絶縁層4a、4b
・・・絶縁層部分、 5・・・配線金属5a、5b・・
・配線金属部分。 ベコ (%、+   S+         1F 〜  1
Nハ          へ 一)                       
  \ノ勺べj %聾へ  \            \〜\   b
へ* 、−へ、/1\ 〈           = づ へ                        
 どへQロ
FIGS. 1(A) to (D) and FIGS. 2(A) to (D) are process charts for explaining the present invention in detail, respectively. 1... Base layer, 2... Resist pattern 3... Hole, 4... Insulating layer 4a, 4b
...Insulating layer portion, 5...Wiring metal 5a, 5b...
・Wiring metal part. Beko (%, +S+ 1F ~ 1
Nha hei)
\ノ勺\\ For the deaf \ \〜\ b
to * , -to, /1\ 〈 = zuhe
Dohe Qro

Claims (1)

【特許請求の範囲】 1、穴の口部の幅が底部の幅より狭い断面形状を持った
当該穴を有するレジストパターンを下地層上に形成する
工程と、該穴を含むレジストパターンの上側に、指向性
の少ない被着方法で、第一被着膜を被着する工程と、指
向性の強い被着方法で第二被着膜を被着する工程と、前
記レジストパターンを溶解して除去して配線を形成する
リフトオフ工程とを含むことを特徴とする配線形成方法
。 2、第一被着膜を絶縁膜とし、第二被着膜を配線金属と
し、該絶縁膜を被着する工程に続いて、該配線金属を被
着する工程を実施することを特徴とする特許請求の範囲
第1項記載の配線形成方法。 3、第一被着膜を絶縁膜とし、第二被着膜を配線金属と
し、該配線金属を被着する工程に続いて、該絶縁膜を被
着する工程を実施することを特徴とすると特許請求の範
囲第1項記載の配線形成方法。
[Claims] 1. A step of forming a resist pattern having a cross-sectional shape in which the mouth of the hole is narrower than the width of the bottom on the base layer; , a step of depositing a first deposited film using a less directional deposition method, a step of depositing a second deposited film using a highly directional deposition method, and dissolving and removing the resist pattern. and a lift-off step of forming the wiring. 2. The first deposited film is an insulating film, the second deposited film is a wiring metal, and the step of depositing the insulating film is followed by the step of depositing the wiring metal. A wiring forming method according to claim 1. 3. The first deposited film is an insulating film, the second deposited film is a wiring metal, and the step of depositing the wiring metal is followed by the step of depositing the insulating film. A wiring forming method according to claim 1.
JP59130403A 1984-06-23 1984-06-23 Wiring formation method Pending JPS618951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59130403A JPS618951A (en) 1984-06-23 1984-06-23 Wiring formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59130403A JPS618951A (en) 1984-06-23 1984-06-23 Wiring formation method

Publications (1)

Publication Number Publication Date
JPS618951A true JPS618951A (en) 1986-01-16

Family

ID=15033448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59130403A Pending JPS618951A (en) 1984-06-23 1984-06-23 Wiring formation method

Country Status (1)

Country Link
JP (1) JPS618951A (en)

Similar Documents

Publication Publication Date Title
JPS5828736B2 (en) How to form a flat thin film
JPH027544A (en) Process of matching and manufacture of column
JPS618951A (en) Wiring formation method
JPH02172261A (en) Manufacture of semiconductor device
JPS63250155A (en) Manufacture of semiconductor device
JPH04199628A (en) Manufacturing method of semiconductor device
JPS62277750A (en) Formation of multilayer interconnection
JPS5950544A (en) Formation of multi-layer wiring
JPH0346977B2 (en)
JPH02129925A (en) Method of forming wiring
JPS60210851A (en) Semiconductor device and manufacture thereof
JPH02111052A (en) Formation of multilayer interconnection
JPS62299051A (en) Formation of electrode of semiconductor device
JPS63133647A (en) Manufacture of semiconductor device
JP2993044B2 (en) Method for manufacturing semiconductor device
JPS63289938A (en) Manufacture of semiconductor device
JPS6362104B2 (en)
JPS6226843A (en) Formation of electrode metal wiring pattern
JPS63237441A (en) Semiconductor device
JPS62136857A (en) Manufacture of semiconductor device
JP3036038B2 (en) Method for manufacturing semiconductor device
JPS62222654A (en) Manufacture of semiconductor device
JPS6149437A (en) Semiconductor device
JPS639952A (en) Manufacture of semiconductor device
JPS63299120A (en) Formation of electrode of semiconductor device