JPS6189622A - Formation of silicon single crystal film - Google Patents
Formation of silicon single crystal filmInfo
- Publication number
- JPS6189622A JPS6189622A JP59211718A JP21171884A JPS6189622A JP S6189622 A JPS6189622 A JP S6189622A JP 59211718 A JP59211718 A JP 59211718A JP 21171884 A JP21171884 A JP 21171884A JP S6189622 A JPS6189622 A JP S6189622A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- single crystal
- substrate
- window openings
- poly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H10P14/3814—Continuous wave laser beam
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3238—Materials thereof being insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3242—Structure
- H10P14/3244—Layer structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3451—Structure
- H10P14/3452—Microstructure
- H10P14/3458—Monocrystalline
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
- H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H10P14/382—Scanning of a beam
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシリコン単結晶薄膜の形成方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for forming a silicon single crystal thin film.
トランジスタ、ＩＣなどの半導体デバイスはシリコン（
Ｓｉ）で代表される単体半界体、ガリウム砒素（ＧａＡ
ｓ＞やインジウム燐（ＩｎＰ ）で代表される化合物半
導体を用いて作られているが、これらのデバイスは何れ
も単結晶からなる薄板を基板とし、薄膜形成技術、写真
食刻技術（ホ１−リソグラフィ）、不純物拡散技術など
を用いて形成されている。Semiconductor devices such as transistors and ICs are made of silicon (
Gallium arsenide (GaA
These devices are manufactured using compound semiconductors such as s> and indium phosphide (InP), but these devices all use a thin single crystal substrate as a substrate, and use thin film formation technology and photolithography technology (Ho1-Phosphate). Lithography), impurity diffusion technology, etc.
ここで大部分のデバイスが作られている半導体はＳｉで
あり、使用される基板（ウェハ）も直径が５インチ或い
は６インチで厚さが約５００μｍと大形のものが用いら
れている。The semiconductor from which most of the devices are made here is Si, and the substrate (wafer) used is also large, with a diameter of 5 inches or 6 inches and a thickness of about 500 μm.
一方、半導体デバイスが形成されるチップの大きさは最
大の・ものでもｌＱ＋ａｍ角であり、一枚のウェハを処
理単位として形成するために、多数の素子が量産されて
いる。On the other hand, the maximum size of a chip on which a semiconductor device is formed is lQ+am, and in order to form one wafer as a processing unit, a large number of elements are mass-produced.
ここで半４体デバイスは単結晶ウェハ上に直接パターン
形成されるが、素子容量の減少や素子間分離耐圧向上な
どの目的には誘電体分甜の構造がとられている。Here, the semi-quadramid device is patterned directly on a single crystal wafer, but a dielectric layer structure is used for purposes such as reducing element capacitance and improving isolation voltage between elements.
すなわち単結晶ウェハ上に二酸化珪素（Ｓｉ０２）など
の絶縁層を形成し、この上に単結晶薄膜を成長せしめ、
これを基板としてデバイスが形成さｄＴ、ている。That is, an insulating layer such as silicon dioxide (Si02) is formed on a single crystal wafer, and a single crystal thin film is grown on this.
A device is formed using this as a substrate.
またη【結晶ウェハ上に二次元のテハ・イスを形成した
後、この上に絶縁層を被）Ｗして層絶縁し、この上に更
にデバイスを形成して三次元構造をとる場合にも絶縁層
上への半ｍ体単結晶イｐｉ膜の成長が必要である。Also, when forming a two-dimensional technology chair on a crystal wafer and then covering it with an insulating layer to insulate the layer, and then forming a device on top of this to form a three-dimensional structure, Growth of a semi-molar single crystal Ipi film on the insulating layer is required.
本発明はかかる目的に使用されるＳ ｉ 薄１模の単結
晶化法Ｑこ関するものである。The present invention relates to a method for single-crystallization of Si thin 1 model used for such purpose.
ご従来の技術〕
熱酸化により二酸化珪素（ＳｉＯ□）からなる絶縁層を
形成したＳ１ウエハに化学気相成長法（ＣＶＤ法）を用
いて一面にポリＳｉＯ薄層を形成し、これにレーザ照射
や電子ビーム投射などの熱エネルギ線を投射して結晶化
することが行われているが、この場合に予め絶縁層に窓
開けしてＳｉ基十反を露出させておき、この状態でポリ
ＳＩ層の形成を行い、熱エネルギ線を投射して加熱し単
結晶化する方法と、絶縁層に窓開けを行わすＳこ熱エネ
ルギ線を投射して単結晶化する方法がある。Conventional technology] A thin poly-SiO layer is formed on one surface using chemical vapor deposition (CVD) on an S1 wafer on which an insulating layer made of silicon dioxide (SiO□) has been formed by thermal oxidation, and this is irradiated with laser. Crystallization is carried out by projecting thermal energy beams such as electron beam projection or electron beam projection. There is a method in which a layer is formed and heated by projecting a thermal energy beam to form a single crystal, and a method in which an S thermal energy beam is applied to open a window in the insulating layer to form a single crystal.
ここて前者の方法は基板の結晶方位がそのまま維持され
て所謂る上ピタキうヤル成長が進行すると云う長所があ
る。The former method has the advantage that the crystal orientation of the substrate is maintained as it is and so-called top-pitched growth proceeds.
第３図は従来行われてきた方法を模式的に示−イーＳｉ
ウェハの部分゛１４面図、また第４図（Ａ ）は］ご開
シナ部分の断面図である。Figure 3 schematically shows the conventional method - E-Si
FIG. 4(A) is a cross-sectional view of the opening portion of the wafer.
ずなわらＳｉウェハｌの上には加熱酸化によって厚さが
５０００人〜１μｍのＳｉＯ２層２が設けられており、
このＳｉＯ２層２には形成するデバイスの規模により異
なるが数μｍ角の窓開は部３が多数個形成されている。On top of the Zunawara Si wafer l, a SiO2 layer 2 with a thickness of 5,000 to 1 μm is provided by thermal oxidation.
This SiO2 layer 2 has a large number of window openings 3 of several μm square, although this varies depending on the scale of the device to be formed.
次に、かかるＳｉＯｚ層２の上に例えば厚さ約４０００
人のポリＳｉ層・１を形成し、熱エネルギ線例えばアル
ゴン（Ａｒ） Ｌ□−ザをＳｉウェハ１の一端より順次
全面に互って走査し、これによりボ’ＪＳｉ層４の単結
晶化を行っていた。Next, on this SiOz layer 2, for example, a layer with a thickness of about 4000 mm is deposited.
A poly-Si layer 1 is formed, and a thermal energy beam, such as argon (Ar) laser, is sequentially scanned over the entire surface from one end of the Si wafer 1, thereby converting the Si layer 4 into a single crystal. was going on.
然しなから、ＳｉＯｚ層２とＳｉウェハ１とては熱電導
率が異なるために同一のレーザパワーでボ゛ＪＳｉ層４
の結晶化を行うことは困難である。However, since the SiOz layer 2 and the Si wafer 1 have different thermal conductivities, it is possible to
It is difficult to perform crystallization of
すなわぢＳｉＯｚ層２の上に形成されているボ・、ＩＳ
ｉ層は下地の熱電導が低いので少ないパワーて溶融して
結晶化するのに対し、窓開は部３は下地の常ハ電専か良
いために結晶化にはより多くのパワーが必要である。In other words, the IS formed on the SiOz layer 2
The I-layer has a low thermal conductivity of the base, so it melts and crystallizes with less power, whereas the window-opening part 3 requires more power to crystallize because the base has a normal heat conductivity. be.
そこでポリＳ１層４の総てを単結晶化するには窓開げ部
３のポリＳ１層を結晶化できる高いレーザパワーで照射
する必要があり、この条件はＳｉＯ２層上のポリＳｉ層
に５よ高すぎるために第４図（Ｂ）に示すように窓開は
部３・の凹部に溶融し１こポリＳｉが落ち込みＳｉＯｚ
層２の肩の部分５が露出し易く、平坦性を低下させると
云う問題がある。Therefore, in order to make the entire poly-S1 layer 4 into a single crystal, it is necessary to irradiate the poly-S1 layer in the window opening 3 with a high laser power that can crystallize it, and this condition requires that the poly-Si layer on the SiO2 layer be Because the height was too high, the window opening melted into the recess of part 3, as shown in Figure 4 (B), and one piece of poly-Si fell down into the SiOz.
There is a problem that the shoulder portion 5 of the layer 2 is easily exposed and the flatness is deteriorated.
〔発明がｊＩＹ決しようとする問題点９以上説明したよ
うに絶縁膜上に形成される８１単結晶層は窓開げ部を設
りてエビクキンヤル成長させたものか特性上イ■れてい
るが、窓開り部とそうでない部分とでは結晶化に要する
パワーか異なるために均一な表面状態か得られないこと
が問題である。[Problems to be Solved by the Invention 9] As explained above, the 81 single crystal layer formed on the insulating film may have been grown in a single-crystal manner with a window opening, or may not be suitable due to its characteristics. The problem is that a uniform surface condition cannot be obtained because the power required for crystallization is different between the window opening part and the window opening part and the non-window opening part.
上記の問題点は絶イフ１摸に複数の居：開ＨＪ部を設け
たシリコン基（反上にポリシリコン膜を形成し、該基板
に熱エネルギ線を投射して窓開り部のソリコン基板を核
として単結晶化を行うに当たり、該基板上に予め一定の
間隔をもつ平行線状の窓開は部を形成し、該窓開げ部に
熱エネルギ線を走査して単結晶化した後、該窓開は部と
直角の方向にエネルギ線を投射して基板全域を結晶化さ
ゼることを特徴とするシリコン単結晶膜の形成力法をと
ることにより解決することができる。The above problem can be avoided if there are multiple cases in one copy: A silicon substrate with an open HJ part (a polysilicon film is formed on the opposite side, and a thermal energy beam is projected onto the substrate to form a silicon substrate with a window opening part. When carrying out single crystallization using the core as a core, parallel linear window openings with a certain interval are formed in advance on the substrate, and after single crystallization is performed by scanning a thermal energy beam on the window opening parts. The window opening can be solved by using a silicon single crystal film formation method characterized by projecting an energy beam in a direction perpendicular to the substrate to crystallize the entire area of the substrate.
本発明は窓開レノ部のポリ３１層を結晶化の開始位置と
してエビタ、１−ンヤル成長させる場合に窓開ジノ部の
結晶化とその他の部分の結晶化とを区別し、まず窓開は
部を結晶化せしめ、これを核としてポリＳｉ層の全面を
１１′Ｌ結晶化するものである。In the present invention, when the poly 31 layer in the window opening part is used as the starting point for crystallization, the crystallization in the window opening part and the crystallization in other parts are distinguished from the crystallization in other parts. The entire surface of the poly-Si layer is crystallized to 11'L using this as a core.
第１図は本発明の実施例で同図（Ａ ）はポリ３１層と
この下に形成されている窓開ＬＪ部との関係を示す部分
平面し１、同図（Ｂ）ばこ、ｎ、に対応する断面図であ
る。Fig. 1 shows an embodiment of the present invention, and Fig. 1 (A) shows a partial plan view showing the relationship between the poly 31 layer and the window opening LJ portion formed below. , is a sectional view corresponding to .
すなわらＳ１ウエハ１の上に形成されているＳｉ０２層
２には一定の間隔を保って直線状の窓開ＬＪ部５が設け
られ、この上にポリＳｉ層４がＣＶＤ法などにより形成
されている。That is, the Si02 layer 2 formed on the S1 wafer 1 is provided with linear window opening LJ portions 5 at regular intervals, and a poly-Si layer 4 is formed on this by CVD or the like. ing.
第１図（Ａ）の破線領域は窓開は部５の位置を示したも
のであり、また実線領域はポリＳｉ層４の上に生じた凹
部６を示している。The broken line area in FIG. 1A shows the position of the window opening 5, and the solid line area shows the recess 6 formed on the poly-Si layer 4.
ここで直線状に形成された窓開は部５の間隔は形成する
デバイスの規模により異なっており、本実施例の場合窓
開は部の幅は５μｍ程度、また間隔は２０μｍ程度にと
っである。Here, the intervals between the portions 5 of the window openings formed in a straight line vary depending on the scale of the device to be formed, and in this example, the width of the window openings is approximately 5 μm, and the intervals are approximately 20 μm. .
そしてＡｒレーザのパワーをｌＯワット（Ｗ）でビーム
径を数μｍに調節し、直線状の窓開は部５に沿ってレー
ザ光を走査し窓開は部５のポリＳｉ層を単結晶化せしめ
る。Then, the power of the Ar laser was adjusted to 10 watts (W) and the beam diameter was adjusted to several μm, and the linear aperture scanned the laser beam along section 5, and the window aperture monocrystallized the poly-Si layer in section 5. urge
次にレーザパワーを５Ｗに落とし、またスポット径も大
きくし、今度は直線状の窓開は部５と直角方向に走査し
てＳｉ０２層２の上のポリＳｉ層４を結晶化させる。Next, the laser power is reduced to 5 W, the spot diameter is also increased, and the linear aperture is scanned in a direction perpendicular to the portion 5 to crystallize the poly-Si layer 4 on the Si02 layer 2.
このように窓開は部５を大きなパワーで先に結−′
晶化し、次にパワーを減じて全面を結晶化させれば従来
のように顕著な凹凸を生ずることなくエピタキシャル成
長を行うことができる。In this way, when opening the window, first connect part 5 with great power.
By crystallizing and then crystallizing the entire surface by reducing the power, epitaxial growth can be performed without producing significant unevenness as in the conventional method.
第２図は別な実施例を示すもので、ＳｉＯ２層に形成し
た窓開は部７とポリ５ｉｌｉｉ４に次工程で形成が予定
されるデバイス位置８との関係を示している。FIG. 2 shows another embodiment, in which the apertures formed in the SiO2 layer show the relationship between portions 7 and device positions 8 to be formed in the poly 5ilii4 in the next step.
そして強いレーザパワーで窓開は部７を矢印９の方向に
走査してエピタキシャル結晶成長を行わしめ、次にパワ
ーを落としてこれと直角方向に走査しデバイス位置を結
晶化させる。Then, the window opening section 7 is scanned in the direction of the arrow 9 with strong laser power to perform epitaxial crystal growth, and then the power is lowered and the window is scanned in a direction perpendicular to this direction to crystallize the device position.
このような方法をとることにより平坦なエピタキシャル
結晶層を作ることができる。By using such a method, a flat epitaxial crystal layer can be created.
以上記したように本発明の実施により、絶縁層の露出等
を伴わない平坦な結晶層を形成することができる。As described above, by implementing the present invention, it is possible to form a flat crystal layer without exposing an insulating layer.
第１図は本発明の詳細な説明図で、同図（Ａ）はＳｉウ
ェハの部分平面図、同図（Ｂ）は断面構造図、
第２図は実施例の平面図、
第３図はウェハ上の窓開は部を示す平面図、第４図（Ａ
）、 （Ｂ）は従来工程を示す断面図である。
図において、
ｌはＳｉウェハ、 ２はＳｉＯ２層、３１Ｌ
ｌ、７は窓開は部、 ４はポリＳｉ層、８はデバイス位
置、
である。
簗１ｇ
（，４）FIG. 1 is a detailed explanatory diagram of the present invention; FIG. 1A is a partial plan view of a Si wafer, FIG. 2B is a cross-sectional structural diagram, FIG. 2 is a plan view of an embodiment, and FIG. FIG. 4 (A) is a plan view showing the window opening on the wafer.
) and (B) are cross-sectional views showing the conventional process. In the figure, l is a Si wafer, 2 is a SiO2 layer, 31L
1, 7 is the window opening, 4 is the poly-Si layer, and 8 is the device position. 1g of bamboo shoots (,4)
Claims (1)
リシリコン膜を形成し、該基板に熱エネルギ線を投射し
て窓開け部のシリコン基板を核として単結晶化を行うに
当たり、該基板上に予め一定の間隔をもつ平行線状の窓
開け部を形成し、該窓開け部に熱エネルギ線を走査して
単結晶化した後、該窓開け部と直角の方向にエネルギ線
を投射して基板全域を結晶化させることを特徴とするシ
リコン単結晶膜の形成方法。A polysilicon film is formed on a silicon substrate in which a plurality of window openings are provided in an insulating film, and a thermal energy beam is projected onto the substrate to perform single crystallization using the silicon substrate in the window openings as a core. Parallel line-shaped window openings with a certain interval are formed in advance on the top, a thermal energy beam is scanned over the window openings to form a single crystal, and then an energy beam is projected in a direction perpendicular to the window openings. 1. A method for forming a silicon single crystal film, characterized by crystallizing the entire area of a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59211718A JPS6189622A (en) | 1984-10-09 | 1984-10-09 | Formation of silicon single crystal film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59211718A JPS6189622A (en) | 1984-10-09 | 1984-10-09 | Formation of silicon single crystal film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6189622A true JPS6189622A (en) | 1986-05-07 |
Family
ID=16610446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59211718A Pending JPS6189622A (en) | 1984-10-09 | 1984-10-09 | Formation of silicon single crystal film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6189622A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62296508A (en) * | 1986-06-17 | 1987-12-23 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893215A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Manufacture of semiconductor singlecrystal thin film |
-
1984
- 1984-10-09 JP JP59211718A patent/JPS6189622A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893215A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Manufacture of semiconductor singlecrystal thin film |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62296508A (en) * | 1986-06-17 | 1987-12-23 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
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