JPS6192065U - - Google Patents
Info
- Publication number
- JPS6192065U JPS6192065U JP17680384U JP17680384U JPS6192065U JP S6192065 U JPS6192065 U JP S6192065U JP 17680384 U JP17680384 U JP 17680384U JP 17680384 U JP17680384 U JP 17680384U JP S6192065 U JPS6192065 U JP S6192065U
- Authority
- JP
- Japan
- Prior art keywords
- package
- integrated circuit
- semiconductor integrated
- circuit device
- uneven
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ，ｂ，ｃはそれぞれ本考案の半導体集
積回路装置のパツケージの一実施例を示す平面図
、側面図、部分拡大平面図、第２図ａ，ｂはそれ
ぞれ第１図ａにおけるセラミツクパツケージの使
用例を示す平面図、側面図および第３図ａ，ｂは
それぞれ従来の半導体集積回路装置のパツケージ
の一例を示す平面図、側面図である。
１，１１…セラミツクケース、２…シールリン
グ、３…ボンデイングパツド、４…端子ピン、５
，６…導電性パツド、７…プリント回路印刷基板
。
1a, b, and c are respectively a plan view, a side view, and a partially enlarged plan view showing an embodiment of the package of the semiconductor integrated circuit device of the present invention, and FIGS. 2a and 2b are respectively the ceramic package shown in FIG. A plan view and a side view showing an example of the use of the package, and FIGS. 3A and 3B are a plan view and a side view, respectively, showing an example of a package of a conventional semiconductor integrated circuit device. 1, 11... Ceramic case, 2... Seal ring, 3... Bonding pad, 4... Terminal pin, 5
, 6... Conductive pad, 7... Printed circuit printed board.
Claims (1)
ラミツク基板を積層焼成した半導体集積回路装置
のパツケージにおいて、前記パツケージの縁辺側
面に凹凸の溝を設け、この凹凸部に導電性のパツ
ドを形成することを特徴とする半導体集積回路装
置のパツケージ。 In a semiconductor integrated circuit device package in which ceramic substrates on which a conductive layer with a predetermined wiring pattern is formed are laminated and fired, uneven grooves are provided on the edge side of the package, and conductive pads are formed in the uneven parts. A package for a semiconductor integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680384U JPS6192065U (en) | 1984-11-21 | 1984-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680384U JPS6192065U (en) | 1984-11-21 | 1984-11-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6192065U true JPS6192065U (en) | 1986-06-14 |
Family
ID=30734387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17680384U Pending JPS6192065U (en) | 1984-11-21 | 1984-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6192065U (en) |
-
1984
- 1984-11-21 JP JP17680384U patent/JPS6192065U/ja active Pending
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