JPS6197854A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to improve the reliability by effective utilization of chips by reducing the area needed to bonding pads by a method wherein those of peripheries along the chip's shorter sides and the chip's longer sides which are larger in distance between arrays and the chip's longer sides are provided with bonding pads. CONSTITUTION:Memory cell arrays 131, 131 and memory cell arrays 132, 132 are arranged with center lines parallel with the longer sides of the chip 11 shifted from each other. Bonding pads 14... are provided in those of peripheries along the shorter sides of the chip 11 and the longer sides which are larger in distance between the longer sides of the chip 11 and the memory cell arrays 131, 131, 132, 132. Then, those regions of peripheries along the longer sides of the chip 11 which are provided with the bonding pads 14... require a width (a) of about 200mum, whereas the width (b) of the regions not provided with the bonding pads 14... can be reduced to about 30mum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to the arrangement of a memory cell array in a semiconductor memory device.

[Technical background of the invention and its problems]

Historically, dynamic RAIVI has adopted an address multiplexing method, in which row and column addresses are input from the same pin and are stored one hour apart, so compared to static RAM, the number of address input pins is lower. The number is l/2.

For this reason, dynamic R up to 16 to 256 bits
AM: 16 bins, 300 mil (7.62m)
Small width line I P (Dual In Line)
) It is now possible to store it in a molded arm cage. Therefore, the IC density of a board on which many ICs are mounted has been improved, and high-density mounting has become possible.

By the way, when classified according to material and manufacturing method, there are ceramic types, T-dip types, and plastic types, but the plastic type is suitable for mass production and can achieve cost reduction. However, in order to further improve the packaging density of an IC board, it is difficult to house an IC chip in a 300-mil wide DIP or cage using a glass type for the following reasons.

First, plastic packages have lower mechanical strength than ceramic packages, so the lead pins must be embedded somewhat inside the cage. Therefore, space must be secured for the lead pins, which limits the width of the IC chip. Therefore, restrictions are placed on the layout of memory cells and peripheral circuits within the chip. This places an upper limit on the chip size, which continues to increase even with the use of fine processing techniques, as the capacity of dynamic RAM increases from 256 bits to IM bits to 4M pits.

This reduces the size of the unit memory cell, and in the case of an 1-transistor, 1-capacitor type memory cell, the area of the capacitor for storing information decreases. Therefore, the data retention characteristics of the dynamic RAM deteriorate and the soft error rate increases, resulting in low reliability and low commercial value.

Also, in the Gerastec type package, is there a connection between the lead pin and the IC chip? Increasing the bonding length of the thin metal wire between the wires and the wires is one of the advantages of thin metal wires!
This is undesirable because it causes poor connection of the LT wire or the bonding part.

If the chip size is small and the distance between the lead pins arranged around the chip and the female landing nodes in the chip can be made small, the layout of the memory cells and zoning nodes in the chip is shown in Figure 3. It's something like this. That is, a plurality of memory cell arrays 2. ... are formed in an array, and the binding pads 3. ... are collectively formed only at the peripheral edge along the short side of the chip 1. In this case, it is advantageous for one circuit operation because the wasted area (periphery along the long side of the chip 1) can be made as small as possible. However, when the memory capacity increases, the tag size increases, and the number of pins increases, a layout as shown in Figure 4 is adopted to shorten the distance between the lead pins and the binding pads. That is, within the rectangular chip 1, the binding pads 3. ... are formed not only at the periphery along the short side of the chip 1, but also at the periphery on both sides along the long side. With such a layout, the area required to form the denting nodes at the periphery along the long sides can be used for the memory cell array and peripheral circuits.

For example, in Figure 4, considering the margin around the pad, the width a of the periphery along the long side of the chip is approximately 200 μm.
Therefore, a 400 μm wide area on each side is wasted just for the bonding. As a result, the width of the memory cell array must be reduced, and the area of the memory cell is reduced, which significantly reduces the reliability of the manufactured product.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device with improved reliability by reducing the area required for the probe arm and making effective use of the chip.

[The Princess of Invention]

In the semiconductor device of the present invention, a plurality of arrays are arranged in such a manner that the center lines parallel to the long sides of the chips of adjacent arrays are shifted from each other along the long sides of the chips. This is characterized by the provision of probes or rads on the peripheral edge along the longer sides, where the distance between the array and the longer side of the chip is greater.

The problem with such a semiconductor device is that the binding pad is arranged only on one side of the periphery along the long side of the chip, which reduces the area wasted by pumping pads and improves the chip. You can effectively use 5g! Product reliability can be improved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, a decoder 12.12 is formed in the center of a rectangular chip 11. Each of the two areas divided by the decoders 12 and 12 has a memory cell array 1.
3. ．． 13. and memory cell array 13. ．． 13. are arranged in two rows along the short side of the chip 11. Mesori cell array 131.13. and memory cell array 13
! , 13. and are arranged with their center lines along the long sides of the chips 11 shifted from each other.

Ponding pad 14. . . . are the peripheral edge along the short side of the chip 11, and the long side of the chip 11 and the memory cell array 13□ among the peripheral edge along the long side.

131, l 3! , J 3! It is located on the side where the distance is greater.

However, in the semiconductor device described above, the distortion occurs in the periphery along the long side of the chip J? landing pad 14. The width a of the region in which the shapes Fy, -g are formed can be reduced to about 30 μm. Since only one side of the periphery along the long side of the chip 11 is substantially used as a bonding pad, the area of the chip 1 can be effectively used as a memory cell array, and the memory cell The size can be increased. Note that by shifting the memory cell arrays, the wiring connecting the arrays is made oblique, but the area required for this wiring increases only slightly.

The storage capacity can be increased due to the above reasons.

Since it is possible to increase the amount of input signals input to the sense amplifier to perform a highly sensitive amplification operation, it is possible to reduce variations in characteristics due to process variations. Also.

It can also accommodate the narrow 300m wide Gerastec package, with lead pins and I-indentation holes 4. It is possible to shorten the length of the wiring with the board, and it is possible to reduce the problem of wiring breakage or poor connection after assembly. Therefore, a highly reliable highly integrated memory IJIc can be realized.

It should be noted that the arrangement of the memory cell array and the binding node is not limited to that shown in FIG. 1, but may be as shown in FIG. 2.

A decoder 12 is formed in the center of the rectangular chip 11, and a memory cell array 13. ．． 134.

13. 13. are arranged with their center lines parallel to the long sides of the terra f11 being shifted from each other.

Dending/Tsudo 14. ... are provided at the peripheral edge along the short side of the chip 11 and the peripheral edge along the long side of the chip 11, whichever has a larger distance from the long side to the memory cell array.

Even with a semiconductor device arranged in this manner, the same effects as in the above embodiment can be obtained.

Although the above description deals with the case where the array group is a memory cell array, the present invention can be similarly applied to circuit blocks such as r-dore arrays and logic circuits.

〔Effect of the invention〕

As described in detail above, the semiconductor device of the present invention has remarkable effects such as reducing the area required for the gonding nozzle, making effective use of the chip, and improving reliability.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the arrangement of a memory IC in an embodiment of the present invention, and FIG. 2 is a memo I in another embodiment of the present invention.
FIGS. 3 and 4 are plan views showing the arrangement of a conventional memo IJIc. FIGS. 11... Chip, 12... Decoder h731sJ
J, , l J, , I J, . . . memory cell array, 14 . . . bonding pad. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 2 Figure 4

Claims (2)

[Claims] (1) In a semiconductor device that has a plurality of array groups divided into a rectangular chip, and bonding pads for connecting the array groups to external circuits are provided on the chip periphery on the outer periphery of the array, the long side of the chip is Multiple rows of arrays are arranged with the center lines parallel to the long sides of the chips of adjacent arrays shifted from each other, and the arrays and chips are arranged at the periphery along the short side of the chips and between the arrays and the chips A semiconductor device characterized in that a bonding pad is provided on a peripheral edge portion having a larger distance from the long side. (2) The semiconductor device according to claim 1, wherein the unit component of the array is a memory element.