JPS619977U - image storage device - Google Patents
image storage deviceInfo
- Publication number
- JPS619977U JPS619977U JP9246684U JP9246684U JPS619977U JP S619977 U JPS619977 U JP S619977U JP 9246684 U JP9246684 U JP 9246684U JP 9246684 U JP9246684 U JP 9246684U JP S619977 U JPS619977 U JP S619977U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frame
- field
- switch
- frame memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Picture Signal Circuits (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第５図は従来の雑音除去装置の構成を示すブロック図、
第２図はテレビジョン信号のインクレース走査を説明す
る図、第３図は被写体が動いた際に発生する二重画像を
説明する図、第４図は従来の二重画像発生防止回路の構
成を示すブロック図、第１図は本考案の実施例のブロッ
ク図、第６図は本考案におけるフレームメモリ、切替ス
イッチ制御回路の一具体例を示すブロック図、第７図は
タイミングチャート、第８、第９図は本考案の第２、第
３の実施例のブロック図である。
２， ７， ３３・・・・・・ゲイン変換器、３，
３２・・・・・・加算器、５・・・・・・フレームメモ
リ、１０．４０・・・・・・切換スイッチ、１１・・・
・・・フレームメモリ制御回路、１６・・・・・・スイ
ッチ切換制御回路、３０・・・・・・ＩＨ遅延回路。FIG. 5 is a block diagram showing the configuration of a conventional noise removal device.
Figure 2 is a diagram explaining increment scanning of a television signal, Figure 3 is a diagram explaining double images that occur when the subject moves, and Figure 4 is the configuration of a conventional double image generation prevention circuit. FIG. 1 is a block diagram of an embodiment of the present invention; FIG. 6 is a block diagram of a specific example of the frame memory and changeover switch control circuit of the present invention; FIG. 7 is a timing chart; , FIG. 9 is a block diagram of the second and third embodiments of the present invention. 2, 7, 33...gain converter, 3,
32... Adder, 5... Frame memory, 10.40... Changeover switch, 11...
. . . Frame memory control circuit, 16 . . . Switch switching control circuit, 30 . . . IH delay circuit.
Claims (1)
ムメモリと、このフレームメモリへの記録及び既にメモ
リに記憶されている１フレーム前の信号（以下フレーム
遅延信号）と１フィールド＋１／２Ｈ（Ｈは水平走査期
間）又は１フィールド−１ ／２Ｈ前のあるいは両者を
混合した信号（以下フィールド遅延信号）の読出を指示
するフレームメモリ制御手段と、上記テレビジョン画像
信号とフィールド遅延信号のどちらか１つを切替え選択
するスイッチと、該スイッチを外部から画像記憶命令が
出た後フィールドの切れ目で切替えるスイッチ制御手段
と、上記スイッチで選択された信号と上記フレーム遅延
信号を被写体の動きに応じて変化する比率で混合加算し
、上記フレームメモリの入力に送る手段を有することを
特徴とする画像記憶装置。Storing one frame of television image signal ・Frame memory, recording to this frame memory, and the signal of the previous frame already stored in the memory (hereinafter referred to as frame delayed signal) and 1 field + 1/2H (H is horizontal a frame memory control means for instructing the reading of a signal (hereinafter referred to as a field delay signal) from 1 field-1/2H before (scanning period) or 1 field-1/2H, or a mixture of both; A switch for switching and selecting, a switch control means for switching the switch at a field break after an external image storage command is issued, and a ratio for changing the signal selected by the switch and the frame delay signal according to the movement of the subject. An image storage device characterized in that it has means for mixing and adding the signals and sending the mixed signals to the input of the frame memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9246684U JPS619977U (en) | 1984-06-22 | 1984-06-22 | image storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9246684U JPS619977U (en) | 1984-06-22 | 1984-06-22 | image storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS619977U true JPS619977U (en) | 1986-01-21 |
Family
ID=30649288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9246684U Pending JPS619977U (en) | 1984-06-22 | 1984-06-22 | image storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS619977U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63287270A (en) * | 1987-05-20 | 1988-11-24 | Sanyo Electric Co Ltd | Noise reducer circuit |
-
1984
- 1984-06-22 JP JP9246684U patent/JPS619977U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63287270A (en) * | 1987-05-20 | 1988-11-24 | Sanyo Electric Co Ltd | Noise reducer circuit |
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