JPS62109152A - Information processor - Google Patents

Abstract

PURPOSE:To obtain an information processor that can discriminate a memory mapped I/O by providing the information on a memory mapped I/O to a page describer and also storing this information in a TLB. CONSTITUTION:An effective address 12 and a real address 14 are stored in an address conversion index mechanism together with an input/output control signal. Then the address 14 is read out of the address 12 when the conversion of address is carried out together with the input/output control signal. When an I/O access is shown, the input/output control signal obtained from an effective address calculating part together with the effective address is switched so as to show an I/O access and sent to a main memory controller together with the real address. The main memory controller performs the switch between the main memory access and the I/O access by the input/output control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a central processing unit in an information processing device, and sometimes to an input/output control mechanism of the central processing unit.

[Conventional technology]

Conventionally, the following two methods have been considered for accessing external input/output devices from a central processing unit.

(1) When the A central processing unit executes an input/output command, it outputs the input/output device number and write/read signals to all input/output devices, and exchanges data with the input/output devices. access by command).

(2) Allocate an input/output device to a part of the address space where the main memory is allocated, and the address output when executing write/read instructions, arithmetic instructions, etc. to the main memory is the address assigned to the input/output device. If there is one, there is a method for exchanging data with the input/output device (access via memory Mabutsu I/O).

Here, the latter memory M/OH1 has the feature that it is possible to specify the input/output device 1'e in the same way that the main memory can be specified as a memory operand for general arithmetic and logic operation instructions, transfer instructions, etc. However, it is effective in high-performance, multi-functional microprocessors.

[Problem that the invention seeks to solve]

However, on the other hand, an interleave configuration method is possible as a speed-up method for the main memory, but such a configuration is difficult for the input/output device, and reading/4I writing fails for both the main memory and the input/output device. In a central processing unit that uses a paging-based virtual memory system and can specify operand addresses in bytes, if an operand spans multiple pages, the I/O/O0 memory space is The behavior of the central processing unit when pages span spans differs depending on the case.In a central processing unit that fully uses the pipeline method, the operand of the n+1st instruction is read before the operand of the nth instruction is written. I/O/
In the case of O0, if this happens, the control of the input/output device may go out of order.In the central processing unit with a memory-mapped I/O configuration, there is no distinction between memory space and I/O/O0 internally, so the control of the input/output device may be disrupted. There are drawbacks such as the difficulty of realizing all the functions of specifying the 3% right relevel for all access execution.

[Means for solving problems]

The above problem is that the central processing unit has memory space and I/O/O
This is due to the fact that 0 cannot be determined. On the other hand, in order to convert a virtual address into a real address in a central processing unit that uses a virtual memory method, a segment descriptor,
Use page descriptors, etc. These descriptors contain information for converting virtual addresses from virtual addresses to Kfl addresses, as well as information for memory preservation. j+, In addition to these pieces of information, it is also possible to have information indicating to which address the I/O device is connected (hereinafter referred to as MPIO information). Therefore, the present invention applies to this MPI
The present invention provides an information processing device f capable of determining memory I/O'i based on O information.

〔Example〕

The invention will be explained with reference to all the drawings.

FIG. 1 is a block diagram of an address variation unit (hereinafter referred to as TLB) in an embodiment of the present invention.

In FIG. 1, numeral 11 is a register (VAR) for storing an effective address (or virtual address) sent from the effective address calculation section.

12 is partial and total removal of the in-page offset of the virtual address (
04c virtual page incense name all multiple memorized, also VAFL1
1a This is a memory that has a comparison function with the virtual page number section. This encoder is used to generate an IJ number (encoding which entry matches with the comparison function of the memory 12). Reference numeral 14 denotes a memory for storing real address information, storage information, and MPIO information corresponding to the entry number matched by the memory 12° encoder 13. 15
is a designated register (abbreviated as RA) that temporarily stores real address information, storage information, and MPIO information read from the memory 14. Reference numeral 16 denotes a register (referred to as TAGR) for temporarily storing incidental information w (hereinafter referred to as tag information) sent simultaneously with the virtual address from the effective address calculation section. 17 is a signal that encodes the tag information in TAGR and indicates the type of access (referred to as access type).
A signal (referred to as M/IO) indicating whether or not Ilo is t
-This is a circuit for generating. Reference numeral 18 indicates entry level information from the instruction execution section and access type ↑R information from the decoder 17.

A circuit for detecting protection exceptions from protection information etc. from the RAR 15 is provided. MPI (J
This circuit completely determines whether the virtual address sent from the effective address calculation unit indicates the memory space or the I/O space based on the information and the M/IO signal from the decoder 17. 1/O is a bus (referred to as ABM) that sends the effective address=tX section to the virtual address '1TLB to the memory control section, and multiplexes and sends from the TLB to the real address all memory control sections. 111 sends tag information from the effective address calculation unit at the same time as the virtual address, and 1゛L
This is a bus for sending tag information at the same time as the destination address. The access signal CI (JAC) from the 112UI/O detection section 19 is sent to the effective address calculation section.

FIG. 2 is a block diagram of the effective address calculation unit, 21i
A bus (EBU8
9:23 is a register (called EATR2) for storing the index 1 straight-7 address, and 9:23 is a register (called EATR2) for storing the index 1 straight-7 address.
24H is a register (called EAT 3) for storing correction values such as bride decrement and post-increment, 25 is a register (called EATR4) for storing a displacement value, and 26 is a register from the instruction analysis section. A bus (called IBUS) for sending the displacement value to the effective address calculation unit, 27 is an EA-8TR
An adder that adds 1 to 1 to 4 in 111 carries and saves (
(referred to as C8A), 28 selects the area of SUm part and Carry part of diC8A by Nf'GRQ value number or N
A multiplexer 29 selects the value of PGR and a constant /O00H', an adder (referred to as CPA) for performing the addition of two inputs selected from the multiplexer 28 VC, and a 2/O base adder 29. A register (called UPAR) for storing the effective address of the memory operand in the first part of the effective address, a 211-digit adder 29
A register (referred to as PFAR) 212 is a calculated effective address bus B for storing all effective addresses of branch destinations or pre-fetch destinations.

This is a bus for sending data to the memory control section, and is connected to the address bus 111 in FIG. 213 is a page boundary detector for fully detecting whether the effective address and the data type of the operand cross the page boundary V; 214 is the virtual page band code of the previous page (from the virtual address to the page 215 is a timing control circuit for the effective address meter nose section. 216 is a register for storing tag information about the operand address sent from the instruction analysis section. Register, 217 digits Tag register 216 information @ fully decoded, data type of operand, signal indicating whether it is an I/O instruction (I/O'ft generating circuit, 218 is TAGR).

The tag information 1TLt3 of 216 is sent to the memory control unit via a bus, and is later stored on the tag bus 1/O in FIG.

In FIG. 31(a), 31 shows the entire address conversion table (referred to as a page table), and 311 shows all one entry (referred to as a page descriptor) of the address change table. Fig. 3 fbl i Fig. 3 shows the detailed configuration of the page descriptor 311 of Fig. 3 +a+. 321 is a bit (referred to as v bit) that indicates whether the contents of this descriptor are valid, and 322 indicates whether the page indicated by this link is I/O
323 is a bit indicating that the page is mapped to an empty stone (called MPIO), 324 is a bit indicating whether the missing page of this descriptor exists in main memory (called P bit),
is a bit (referred to as the A bit) indicating whether the page indicated by this descriptor has been referenced by the central processing unit, and 325 is a bit indicating whether or not the page indicated by this descriptor has been rarely written to by the central processing unit. ) (referred to as W bit), 326
[The maintenance information for the page indicated by this descriptor, 327 indicates whether the page indicated by this descriptor is in memory space or I/O/O0
This is the actual address indicating what address it will be mapped to.

Next, the operation of the non-embodiment VC3 will be explained.

As shown in FIG. 4, the central processing unit in this embodiment VC2 includes an instruction analysis section 43. Effective address calculation unit 44°address conversion unit 45. Main memory control unit 46. Instruction execution unit 47. It consists of each unit. Each unit near address bus 41,
1” bus 42, I bus 48, and E bus 49.

The instruction analysis unit 43 decodes the n instruction loaded from the main memory, and the instruction execution unit 47 decodes the instruction +[T! It is converted into a format that can be processed and entered into the instruction execution unit 47. If the instruction analyzed by the instruction parsing unit 13 has an operand for memory or 1/O space, all effective information (index value, base value, displacement value, etc.) necessary for calculating the effective address of that operand is It is sent to the address calculation section 44. The effective address calculation unit 44 calculates the invalid address bus based on the information necessary for calculating the effective address sent from the instruction analysis unit 43 and sends the effective address to the address conversion unit 45. The address conversion unit 45 converts the effective address sent from the effective address calculation unit 44 into a real address and sends it to the main memory control unit 46. The main memory control unit 46 accesses the main memory or all input/output devices based on the real address sent from the address conversion unit 45.

The instruction execution section 47 sends all information read from the main memory or input/output device to the instruction execution section when reading an operand, and writes the information sent from the instruction execution section 47 to the main memory or input/output device when writing an operand. The instruction is executed according to the instruction decoding information sent from the section 43.

The address bus 41 is used to transfer the effective address from the effective address calculation section 44 to the address translation section 45, and also to transfer all addresses from the address translation section 45 to the main memory control section 46. Also.

The tag bus 42 is a bus used in correspondence with the address bus 41, and is a bus for transferring all information associated with the effective address and real address on the address bus 41. The information 51 transferred to the tag bus 42 includes the following information.

1, bit2-3...operand data length 2
, bit9...M/I (Jt indicates.

3, bitIQ... NPG 4, bit 11-12...--Access
type 5, bit 13-AJ/R 1...Indicates that it is an effective address (virtual address) 0...Indicates that it is a real address.

The operation of the CPU having the above-described configuration when all instructions having operands for the memory or I/(J space) are executed will be briefly explained below.

When the instruction analysis unit 43 analyzes the instruction, it reads ti of the general-purpose register.
Information necessary for effective address calculation such as ll, index 1 shift, displacement 1 shift, etc. 6EBUS (21 in Figure 2, 49 in Figure 4), IBUS (2 in Figure 2)
6. The register EAT 1 of the effective address calculation section is set by 48) in FIG. EATR2, EATR3, EATR4 (
22.23, 24.25) in Figure 2). and accompanying information about the operand (access type, data length,
Information about memory space or 1/(1) space (M/IO), etc.
- Send T'L'AGR161c.

The effective address calculation unit 44 uses EATRl and EATR2°E.
ATR3, EATR4 general-purpose register value index 1, displacement value, etc.? Carry save adder 27. Addition is performed using the carry groper gate adder 29, and the effective address as the addition result is expressed as (JPA
Store in R2/O. Then, the tag information in '1' TAGR1G is decoded to obtain the data length, and the page boundary detector 213 detects whether or not it straddles a page boundary from the effective address and data length.Then, the following 3 What is Toshi's @work?

1. In the case of memory space access, the M/IO information of the TAGR 216 is 1'', indicating that it is a memory space access, and the l0AC decoding from the address conversion unit 45 [112° in FIG. 1 and 219 in FIG. 2] is O
” (indicating that memory is not available),
First, the effective address of the memory operand n stored in 0PAR2/O is output to the address bus 212 and sent to the address conversion section 45. At the same time, the tag information of the TAGR 216 is also output to the tag bus 21B and sent to the address conversion section 45.

Next, the start address of the next page located at the page boundary is calculated. Calculate this g' first (JPAB2/O
virtual page number ((JPAR bits 12-3
1) Store data in the gold NPGR 214, and then store the virtual page number and lower bits O to 11 in the NPGR (signal 220).
Data 221 and constant 000, which are the combination of values with 0 added to
Input 0/O00H to the adder 29 In this embodiment, since the page size is assumed to be 4 bytes, the number /O00I-1 is added to calculate the start address of the next page] .

Then, as a JO calculation result, the start address of the page of the arrow is outputted to the address bus 212 and sent to the address conversion unit 45. At the same time, the tag information of TAGR216 is also transferred to the tag bus 218.
and sends it to the address conversion section. At this time, tag information b
Set it9(NPG)t to "1".

2 In the case of memory Matsubuto I/O, the tag information M/IO of the AGR 216 "1" indicates the memory space, and the I(J
When the AC signal 219 is '1'' (indicating that it is a memory I/O), the effective address of the memory operand stored in the JPAR2/O is output to the address bus 212 and addressed. At the same time, the tag information of K TAea 216 is also output to the tag bus 218 and sent to the address conversion unit 45. At this time, the tag information kl
/IQ f″′0” and send. In this way, an access to the 2D memory space is converted to an access to the 1/U space.

3, I/(TAGR216 for -1 access
(7) Evening information @ M/I (0 if J is “O”)
The effective address of the 0 operand stored in PAR2/O is output to the address bus 212 and sent to the address converter 45. At the same time, the tag 1 information of the TAGR 216 is also output to the tag bus 218 and sent to the address conversion section 45.

TLBi-1 internal address comparison unit 121C virtual page number, data memory unit 14 contains real page number, protection information, MPIOii! Memorize the i-report. In an information processing device that fully adopts the virtual memory method, the page table 31 is placed above the cloud.
．． Page descriptor 32 Rich, these descriptors include ′, 〈
Address 327. Contains protection information 326, etc. And in order to speed up the virtual address → virtual address conversion,
A copy of the information in the segment note link and page descriptor is stored in the 1TLB. In the present invention, MP is included in the page descriptor 32.
It has IO information 323, and if this IO descriptor is '1', it indicates that the page indicated by this page descriptor is mapped during I/O/O, and if it is 0', it indicates that it is a memory space. show.

This MPI is stored in the LB.

The effective address (virtual address) sent from the effective address calculation section is stored in the VARIIK bath 16.

It is stored in the tag tri T'L''AGR, 16 that is sent at the same time.The part excluding the in-page offset (VARbit□~11)'lt of VARII (bits 12-31 of VARII) (referred to as virtual page number) TLB
If there is a matching virtual page number 6fl, an entry 6RAR15 of the data memory section of '1' LB corresponding to that virtual page number is sent.

This data memory section contains real page numbers, protection information, I/O
O information is stored.

Read R, AR, 15 page number [ru mountain bi
t12-31 is the intra-page offset of the virtual address stored in VARII2) (VARbito-3
1) to form a real address bus 111
and sent to the main memory controller.

The protection information (RAR bits 2 to 11) in the RAR 15 is sent to the maintenance check mechanism 18.

Information such as the access type decoded by the decoder 17 from information in the protection check contact T'l'AGR 16 and protection information from the RAR 15.

It checks whether the access is appropriate based on information such as the execution level and the like from the instruction execution unit, and if a protection exception is detected, it is notified to the instruction execution unit.

RAR15 Nakanol/O (17th report (BARbitO) (M
The PI (referred to as J) is sent to the UIU detection unit 19.

I/O detection unit is MP I Ofj5″″l’ when T
Set the M/IO information of TAGR16 to @0" to indicate the I/O space value and send it to the main memory control unit f. Also, when MPIO is L", set l0AC="l" to EAU and send it to the memory Matsubutsu I/O let them know that it is. TTAGR1/
The information on O is sent at the same time as the real address is sent to the main memory controller. At this time, as mentioned above, the memory Matsubuto I/O
In this case, the M/IO information @ is changed to '0'' to indicate I/O space, and the V/R information (signal indicating whether it is a virtual address or a real address) is changed to * 0 # to indicate a real address. Instead, it is output to TBUS and sent to the main memory control unit.The main memory control unit uses the sent real address and tag information to fully access the memory space I/(J space.M/
When the IQ information indicates Ilo, C''''O'') H1 real address '1 is output as the I/O boat address and accesses the entire I/O space. When the I/C1 report outputs the memory space, C'
"1") fl, outputs the real address as the main memory address and accesses the memory space.

〔Effect of the invention〕

As explained above, by making the memory mapped I/O information wait for the page descriptor VC and storing it also in the TLB, memory mapped I/O information can be stored in the central processing unit.
The main memory controller can switch to the memory operand access mapped to the I/O space and perform input/output 1tt-access. By separating memory access and I/O access, the first drawback (interleave configuration method is possible as a speed-up method for the main memory, but h is difficult for input/output devices) is solved.

Also, the effective address calculation unit is mapped from TLB to memory map)
The second disadvantage of receiving I/O information (in a central processing unit that uses a virtual storage system based on the paging method and can specify operand addresses in units of bytes, there is a possibility that operands may span multiple pages; This solves the memory problem I/(the operation of the central processing unit differs between pages in J space and memory space).

[Brief explanation of drawings]

FIG. 1 is a block diagram of an address translation section in an embodiment of the present invention, FIG. 2 is a block diagram of an effective address calculation section in an embodiment of the present invention, and FIG. 3(a). [bl H Embodiment of the present invention VCS - address fm table and page descriptor format diagram; Figure 4 is a plotter diagram showing the configuration of the central processing unit in the embodiment of the present invention; Figure 5 is a diagram showing the configuration of the central processing unit in the embodiment of the present invention; In the format diagram showing the information held by the tag bus in the embodiment, 0 11... Effective address register, 12 River...
Memo')s 13...Encoder, 14・Mountain...Memory% 15...Register, 16・Mountain...
・Tag register, 17... Decoder, 18...
...Detection circuit, 19...Decision circuit. 7'nee＼ Agent Patent Attorney Susumu Uchihara, /':'T,',
I-,-',゛('--Lori mouth. To Kudonige N → Mu4W

Claims (1)

[Claims] An address conversion pulling mechanism, an effective address calculation unit that generates an input/output control signal for switching between main memory access and I/O access and also generates an effective address, and an effective address calculation unit that switches between main memory access and I/O access using the input/output control signal. a main memory controller, which stores effective addresses and real addresses in the address conversion indexing mechanism and also stores input/output control signals, reads the real address from the effective address when address conversion is performed, and controls the input/output. When reading signals to indicate I/O access,
The input/output control signal obtained together with the effective address from the effective address calculation unit is switched to indicate I/O access and sent together with the real address to the main memory control device, and the main memory control device uses the input/output control signal to control the main memory. Access and I
An information processing device characterized by switching /O access.