JPS6211018Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that operates with a safe bias and is suitable for high frequency use.

Conventionally, for example, in most cases of microwave transistors, a semiconductor chip is mounted on a package. Efforts are being made in design to reduce the grounding inductance L as shown in FIG. Also, apart from this,
For example, the field effect transistor (FET) shown in the figure requires two power supplies, one for the gate and one for the drain, but as shown in Figure 2, the source can be grounded at high frequencies via a capacitor C. However, in terms of direct current, the required potential is set by the resistor R _S , and this is applied to the gate bias voltage via the resistor R _G.
If a so-called self-bias method is adopted in which voltage is applied as V _GS , only one power supply is required.

In the self-bias method, when the source of the FET is grounded via a capacitor, it is the same as in the normal case that the higher the frequency band used, the more effort must be made to reduce the grounding inductance.

FIG. 3 is a plan view of the main part of a small output power FET, and FIG. 4 is a side view of the main part.

In the figure, 1 is a heat sink/high frequency ground terminal made of a conductor such as copper, 2 is a ceramic part, 3 is a semiconductor chip, 4 is a capacitor, 5 is a source package lead (external connection terminal), 6
Reference numeral 7 indicates a drain package lead, 7 indicates a gate package lead, and 8 indicates a connection line such as a gold wire or gold ribbon.

In this manner, in the case of a small output transistor, if the capacitor 4 for high frequency grounding is placed and connected immediately next to the semiconductor chip 3, the grounding inductance is small and good grounding is possible.

However, when it comes to high-output transistors that require comb-shaped electrodes, the chip itself is long, so even if a capacitor is placed right next to such a chip, the distance from the active area near the center of the chip to the capacitor is very long. Since the distance becomes large, the grounding inductance also becomes large, and high frequency characteristics deteriorate, making it impossible to obtain sufficient gain.

The present invention provides a semiconductor device in which high-frequency grounding can be achieved through a capacitor without increasing the grounding inductance even in the case of a high-output power transistor having a long semiconductor chip. This will be explained in detail.

In developing the present invention, as shown in FIG.
are arranged in series so that their longitudinal directions cross the direction connecting the leads 7 and 6. The reason for this is that it was considered that the impedance conditions to all operating regions would be the same regardless of whether the connecting wires were drawn out from the central portion or the end portions of the semiconductor chip 3.

However, normal high-output transistors have extremely low input impedance. 6th
The figure illustrates the S-parameter of the GaAs power FET shown in FIG. Therefore, if the lead on the input side becomes long and the inductance increases, it will enter a region where it is difficult to achieve matching, making it difficult and almost impossible to achieve a wide band.

Therefore, as shown in Figure 7, a capacitor C' corresponding to the inductances L ₁ and L ₂ was inserted into the gate on the input side to facilitate matching. ′ must be carefully considered.

FIG. 8 is a plan view of essential parts of an embodiment of the present invention,
The same parts as those described in connection with FIG. 5 are indicated by the same symbols. 9 is a cross-sectional view taken along line A-A', and FIG. 10 is a cross-sectional view taken along line B-B'.

This embodiment differs from the device shown in FIG. 5 in that a capacitor 4' is formed by separating the metal pattern formed on the surface of the dielectric piece on which the capacitor 4 is formed. ’ is the seventh
The circuit connection is made so that it functions as the input side impedance matching capacitor C' shown in the figure. Since the capacitors 4 and 4' are both grounded, the back surface of the dielectric piece,
That is, a common metal pattern is formed on the surface to which the heat sink/high frequency ground terminal is fixed, and the metal pattern is used for fixing. in this way,
One of the features of the present invention is that the capacitor 4 for high frequency grounding and the capacitor 4' for impedance matching are arranged at the same location. GaAs power FET with a gate width of 10 [mm] to which the present invention is applied
The S-parameters are as shown in FIG. 11, making it extremely easy to match, and since the source inductance has become smaller, the small signal gain has improved by 2 [dB].

As can be seen from the above explanation, according to the present invention, in a high-output high-frequency semiconductor device that requires a comb-shaped electrode, the package lead for the gate on the input side and the drain on the output side can be used. A capacitor and a semiconductor chip are arranged in order between the package lead and the input side when viewed from the input side, and the capacitor consists of one for high frequency grounding and one for input side impedance matching. The conductor is divided into a plurality of parts and arranged adjacent to the semiconductor chip between the high-frequency grounding part and the semiconductor chip, and from there the gate package lead is connected to the semiconductor chip. Alternatively, no matter which part of the semiconductor chip the wires are drawn out from, all the wires will be drawn out uniformly and under the same conditions, and since the shortest distance can be taken, the inductance can be kept to a minimum and high frequency grounding can be achieved. In addition, since input side impedance matching can be achieved, it is possible to obtain a device with good high frequency characteristics over a wide band.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a normal FET, Figure 2 is a circuit diagram of an FET with a self-bias configuration, Figure 3 is a plan view of the main parts of the FET shown in Figure 2 as a device, and Figure 4 is a circuit diagram of a FET with a self-bias configuration. Figure 3 is a side sectional view of the main part of the device, Figure 5 is a plan view of the main part of the device that is the basis of this invention, and Figure 6 is a side sectional view of the main part of the device.
The figure shows the Smith equation representing the S-parameters of the device in Figure 5.
Figure 7 is a circuit diagram of a device that matches the impedance on the input side, Figure 8 is a plan view of essential parts of an embodiment of the present invention, and Figure 9 is a cut along line A-A' in Figure 8. 10 is a cutaway view taken along line BB' in FIG. 8, and FIG. 11 is a Smith chart showing the S-parameters of the apparatus shown in FIGS. 8 to 10. In the figure, 1 is a heat sink and high frequency ground terminal, 2 is a ceramic part, 3 is a semiconductor chip,
4 and 4' are capacitors, 5 is a source package lead, 6 is a drain package lead, 7 is a gate package lead, and 8 is a connection line.

Claims (1)

[Scope of utility model registration request] A capacitor and a semiconductor chip are arranged in order from the input side between the gate package lead on the input side and the drain package lead on the output side, and the capacitor is used for high-frequency grounding of the transistor and for the input side. The input side impedance matching device is divided into a plurality of pieces and arranged adjacent to the semiconductor chip between the high frequency grounding device and the semiconductor chip. A semiconductor device characterized by: