JPS62110331A - Coding and decoding device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for encoding and decoding error correction codes in digital signal transmission and recording/reproducing threads.

2. Description of the Related Art In recent years, transmission speeds and recording densities have been increasing at a remarkable rate in various digital signal transmission and recording/reproduction systems.

Accordingly, error correction codes and their encoding/decoding devices for detecting and correcting code errors that occur due to higher speeds and higher densities are becoming increasingly important.

Hereinafter, with reference to the drawings, Reed-Solomon code R8 (20
, 16) will be explained.

Now, FIG. 3 shows the configuration of the above-mentioned conventional encoding/decoding device. In FIG. 3, 1 is an encoding input terminal, 3 is an erasure correction circuit, and 4 is an encoding output terminal. , 5
is a decoding input terminal, 6 is an erasure position detection circuit, 7 is an erasure position polynomial calculation circuit, 8 is a decoding output terminal, and 1o is an encoding circuit. FIG. 4 is a diagram showing an example of the configuration of the encoding circuit 1o, in which 11 to 14 are registers, 15 to 18 are adders, and 19 to 22 are coefficient units.

The operation of the conventional encoding/decoding device configured as described above will be explained below.

First, in the case of R8 (20, 16) code encoding processing, the information symbols sequentially input to the encoding input terminal 1 are added to the encoding circuit 1o, and 4 check symbols are generated for 16 information symbols. After being added, it is output to the encoding output terminal 4.

The encoded signal is applied to the decoding input terminal 5 after passing through a transmission system or a recording/reproducing system. When an error occurs while passing through the transmission system or recording/reproducing system, its position is first determined by the erasure position detection circuit 6, and then the error is erased using the coefficients of the erasure position polynomial calculated by the erasure position polynomial calculation circuit 7. Corrected by the correction circuit 3. The corrected signal is output from the decoding output terminal 8. (Regarding the encoding process, for example, [Decoding Procedure for the Lead Solomon Code)
(R,S,Lim”A DecodingProc
edure for the Reed -3o
lomonCodes'' NASA Tech,
Pap, 1286 197B-8), etc., and regarding erasure correction processing, for example, "Implemental
Opreed-Solomon Eraser-Correcting Decoder for Iblist Coding
Scheme” (F-W, FOX at, al, “Imp
remention of Ree4-3olomo
n Krasure-CorrectingDecod
er ro'r 1 (ybrid Coding S
cheme “IK’EI!: Trans, V
Problems to be Solved by the Invention However, in the above configuration, a dedicated circuit for encoding is essential, and as a result, the scale of the device is reduced. This has been a major problem in reducing the size and cost of devices.

In view of the above-mentioned problems, the present invention provides an encoding/decoding device that does not have a dedicated circuit for encoding, so the scale of the device can be small, and is suitable for downsizing and cost reduction. It is.

Means for Solving the Problems In order to solve the above problems, the encoding/decoding apparatus of the present invention regards the position of the test symbol to be added by the encoding process as the vanishing position, and calculates the position obtained by calculation in advance. It is equipped with a read-only memory that stores the coefficients of the erasure position polynomial, and uses an erasure correction circuit connected to this by a changeover switch to perform erasure correction processing on the input code word. It is equipped with a configuration for realizing processing.

Effect of the Invention With the above-described configuration, the present invention utilizes the erasure correction circuit for encoding processing, thereby eliminating the need for the encoding circuit, which has been indispensable in the past, and making it possible to reduce the scale of the apparatus.

Embodiment Below, regarding an encoding/decoding device according to an embodiment of the present invention,
This will be explained with reference to the drawings. FIG. 1 shows the configuration of a lead encoder/code R5 (20, 16) encoding/decoding apparatus in an embodiment of the present invention. In Figure 1, 1 is an encoding input terminal, 2 is a read-only memory, 3 is an erasure correction circuit, 4 is an encoding output terminal, 6 is a decoding input terminal, 6 is an erasure position detection circuit, and 7 is an erasure position polynomial. The arithmetic circuit, 8 is a decoding output terminal, and 9a to 9G are three interlocking type changeover switches. Of these, read-only memory 2
, and the three interlocking type changeover switches 9a to 9C are all the same as those shown in the example of the conventional encoding/decoding apparatus.

Regarding the encoding/decoding device configured as above,
The operation will be explained below using FIGS. 1 and 2.

The Reed-Solomon code R3 (
20, 16), one block is composed of 26 information symbols and 4 check symbols as shown in FIG.

Now, if we consider the state of the block before encoding, the information symbols indicated by DO to D15 in Figure 2 have already been given, but the positions of the check symbols indicated by PO to P3 are blank. This condition can be viewed in another way.
For example, it can be said that this is completely equivalent to a state in which erasure occurs exactly at the position of the check symbol in the decoding process.

Therefore, erasure correction processing in which the erasure position is fixed at the position of the check symbol can be regarded as encoding processing.

Therefore, first, the information symbol inputted from the encoding input terminal 1 shown in FIG. 1 is inputted to the erasure correction circuit 3 through the changeover switch 9C. At the same time, the coefficients of the erasure position polynomial, which are calculated and stored in the read-only memory 2 in advance by regarding the test symbol position as the erasure position, are input to the erasure correction circuit 3 through the changeover switch 9b. In the erasure correction circuit 3, encoding processing by erasure correction is performed, and the signal to which the check symbol has been added is outputted to the encoding output terminal 4 through the changeover switch 9a.

The decoding process in this embodiment is similar to the decoding process in conventional encoding/decoding devices, and errors that occur when passing through the transmission system or recording/reproducing system are first detected by the erasure position detection circuit 6. Its position is determined, and then it is corrected by the erasure correction circuit 3 using the coefficients of the erasure position polynomial calculated by the erasure position polynomial calculation circuit 7.

The signal that has been corrected is output from the decoding output terminal 8.As described above, according to this embodiment, by providing the read-only memory storing the coefficients of the erasure position polynomial calculated in advance and the erasure correction circuit. Encoding processing can be performed at relatively high speed without using a dedicated encoding circuit.

Effects of the Invention As described above, the present invention regards the position of a check symbol to be added by encoding processing as an erasure position, and includes a read-only memory that stores coefficients of an erasure position polynomial obtained by calculation in advance. By realizing encoding processing using the erasure correction circuit connected to this, there is no need for a dedicated circuit for encoding, and therefore the scale of the equipment can be reduced, leading to miniaturization and lower cost. This makes it possible to realize an encoding/decoding device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an encoding/decoding device in an embodiment of the present invention, FIG. 2 is a configuration diagram of a code in an embodiment of the present invention, and FIG. 3 is a conventional encoding/decoding device. FIG. 4 is a block diagram showing the configuration of the encoding device. FIG. 4 is a block diagram of the encoding circuit in FIG. 3. 2...Read-only memory, 3...Erasure correction circuit, 6...Erasure position detection circuit, 7...Erasure position polynomial calculation circuit, 9a to 9C...3 Interlocking type changeover switch.

Claims (1)

[Claims] To perform the decoding process, there is an erasure position detection circuit, an erasure position polynomial calculation circuit that calculates the coefficients of the erasure position polynomial from the detected erasure position, and an erasure position polynomial calculation circuit that calculates the magnitude of erasure from the coefficients of the erasure position polynomial and performs correction. It is equipped with a correction circuit and a read-only memory that stores coefficients of an erasure position polynomial obtained by calculation in advance, regarding the position of a check symbol to be added by encoding processing as an erasure position, and the read-only memory An encoding method characterized in that encoding processing is realized by performing erasure correction processing on a code word input from a code input terminal using the erasure correction circuit connected to a memory by a changeover switch. decoding device.