JPS62111450A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62111450A
JPS62111450A JP25107585A JP25107585A JPS62111450A JP S62111450 A JPS62111450 A JP S62111450A JP 25107585 A JP25107585 A JP 25107585A JP 25107585 A JP25107585 A JP 25107585A JP S62111450 A JPS62111450 A JP S62111450A
Authority
JP
Japan
Prior art keywords
conductor
wiring
wirings
conductor wirings
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25107585A
Other languages
Japanese (ja)
Inventor
Takeshi Konno
今野 毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP25107585A priority Critical patent/JPS62111450A/en
Publication of JPS62111450A publication Critical patent/JPS62111450A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To eliminate cross talk between telephone circuits, by arranging a conductor wiring, which is connected to a semiconductor substrate, between neighboring conductor wirings. CONSTITUTION:First and second conductor wirings 11 and 12 for signal lines are formed on an insulating film 14 on the surface of a silicon substrate 13. A third conductor wiring 15 is located between the conductor wirings 11 and 12 and kept at the same potential as that of the silicon substrate 13. Most of electric lines of force generated from the conductor wirings 11 and 12 are concentrated between the conductor wirings 11 and 12 for signal wiring and the third conductor wiring 15. The electric lines of force between the conductor wirings 11 and 12 for the signal lines are negligible. Therefore, the relation of the magnitudes of stray capacitances C11, C12 and C13 becomes as follows: C11 C12>>C13. Thus, the cross talk characteristic of the device is improved to a large extent.

Description

【発明の詳細な説明】 産業−1−の利用分野 本発明は、電話交換等、主として音声通信分野において
、複敷チャンネル間のリンクを司る半導体装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Application of Industry-1- The present invention relates to a semiconductor device that controls links between multiple channels, mainly in the field of voice communications such as telephone exchanges.

従来の技術 従来のこの種半導体装置について、第2図を用いて説明
する。第2図はN[118化したMO8型半導体装置の
斜視図で、1はシリコン基板であり、Nチャンネルの場
合はP型、Pチャンネルの場合はN型の各シリコンウェ
ーハを使用する。2はシリコン基板1七に形成されたフ
ィールI−酸化膜であり、膜厚は通常1μmn前後であ
る。3,4はアルミニウムの蒸着膜等で構成された導体
配線である。
2. Description of the Related Art A conventional semiconductor device of this type will be described with reference to FIG. FIG. 2 is a perspective view of an MO8 type semiconductor device converted into N[118], in which 1 is a silicon substrate, and P-type silicon wafers are used for an N-channel, and N-type silicon wafers are used for a P-channel. 2 is a FIEL I oxide film formed on the silicon substrate 17, and the film thickness is usually around 1 μm. Reference numerals 3 and 4 denote conductor wirings made of a vapor-deposited aluminum film or the like.

導体配線S3,4の線幅および線間ギャップは、各々数
μ田であり、これらの寸法はますます縮小する傾向にあ
る。当然のことながら、この2線間には浮遊容ft C
1が存在し、そのギャップが縮小すれば、それに応じて
増加する。例えば、これらの導体配線3,4に電話回線
(A)(B)が接続された時、電話回線(A)(B)間
には主として浮遊容置C,を通したクロストークが生じ
る。実用上許容されるクロストークの量は、音声周波数
帯域で約−90d B以上である。この値を上記の配線
寸法下で実現することは非常に固壁な問題である。
The line width and interline gap of the conductor wirings S3 and S4 are each several micrometers, and these dimensions tend to become smaller and smaller. Naturally, there is a floating capacity ft C between these two wires.
1 exists and the gap decreases, it increases accordingly. For example, when telephone lines (A) and (B) are connected to these conductor wirings 3 and 4, crosstalk occurs between the telephone lines (A) and (B) mainly through the floating container C. The amount of crosstalk that is practically acceptable is about -90 dB or more in the audio frequency band. Achieving this value under the above wiring dimensions is a very difficult problem.

発明が解決しようとする問題点 このように上記従来の構成では、ますます微細化する半
導体装置において、隣接する信号配線間の、主として容
置結合によるクロストークを無くすることができないと
いう問題があった。
Problems to be Solved by the Invention As described above, the above-mentioned conventional configuration has a problem in that it is not possible to eliminate crosstalk between adjacent signal wirings mainly due to volumetric coupling in semiconductor devices that are becoming increasingly finer. Ta.

問題点を解決するための手段 」二l紀問題点を解決するため、本発明の半導体装置は
、隣接して位置する信号線用の第1及び第2の導体配線
間に、半導体基板と接続された第3の導体配線を配置し
たものである。
Means for Solving the Problems In order to solve the second generation problems, the semiconductor device of the present invention includes a semiconductor substrate and a connection between first and second conductor wirings for signal lines located adjacent to each other. This is the arrangement of the third conductor wiring.

作用 北記構成によれば、第3の導体配線がシールド作用を行
い、クロストークが減少する。
According to the configuration described above, the third conductor wiring performs a shielding function, reducing crosstalk.

実施例 以下、本発明の一実施例を第1図に基づいて説明する。Example An embodiment of the present invention will be described below with reference to FIG.

第1図は本発明の一実施例における半導体装置の斜視図
で、この半導体装置はMOS型であり、簡略化して図示
している。第1図において、11゜I2は信号線用の第
1.第2の導体配線であって、シリコン基板13の表面
に形成された二酸化シリコン11りなとのシリコン系絶
縁膜111の上に形成されている。15は第3の導体配
線であり、第]、第2の各導体配線I+、+2の中間に
位置し、コンタクトウィンドウ16により、シリコン系
絶縁膜14を貫通して、シリコン基板I3の不純物濃度
よりやや濃い拡散領域I7に接続されている。したがっ
て、第3の導体配線15は、シリコン基板13と同一電
位に保持される。C11は導体配線II、15間の浮遊
容量、C12は導体配線12.15間のンl遊容址、C
0,は導体配線11.12間の浮遊容量である。
FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention. This semiconductor device is a MOS type and is shown in a simplified manner. In FIG. 1, 11°I2 is the first .I2 for the signal line. The second conductor wiring is formed on a silicon-based insulating film 111 of silicon dioxide 11 formed on the surface of the silicon substrate 13. Reference numeral 15 denotes a third conductor wiring, which is located between the first and second conductor wirings I+ and +2, penetrates the silicon-based insulating film 14 through a contact window 16, and is lower than the impurity concentration of the silicon substrate I3. It is connected to a slightly dense diffusion region I7. Therefore, the third conductor wiring 15 is held at the same potential as the silicon substrate 13. C11 is the stray capacitance between the conductor wiring II and 15, C12 is the stray capacitance between the conductor wiring 12 and 15, and C
0, is the stray capacitance between the conductor wirings 11 and 12.

次に動作を説明する。(8号線用の各導体配a11゜1
2から発生する電気力線のほとんどは、各信号線用の導
体配線11. +2と第3の導体配線15との間に集中
し、各信号線用の導体配線11.12間のそれはほとん
ど無視できる程度となる。従って、浮遊容量C1,,C
1□、C工、の大小関係は、C工、≠C1□)C10と
なり、更に第2図に示した従来例の場合との関係におい
ても、各浮遊容量の大小関係で。
Next, the operation will be explained. (Each conductor arrangement for line 8 a11゜1
Most of the electric lines of force generated from the conductor wiring 11.2 for each signal line. +2 and the third conductor wiring 15, and the concentration between the conductor wirings 11 and 12 for each signal line is almost negligible. Therefore, stray capacitance C1,,C
The magnitude relationship between 1□ and C is C10,≠C1□)C10, and also in relation to the conventional example shown in FIG. 2, the magnitude relationship of each stray capacitance.

C工)C1,なる関係を満足することは容易に実現でき
る。
C) It is easy to satisfy the relationship C1.

以−ヒのことから、信号線間の浮遊容量に起因するロク
ストーク特性は、第3の導体配1IAisの設置によっ
て大幅に改善されることが期待できる。
From the above, it can be expected that the roxtalk characteristics caused by stray capacitance between signal lines will be significantly improved by installing the third conductor arrangement 1IAis.

発明の効果 以上述べたように本発明によれば、きわめて簡単かつ実
施容易な構成で、クロス1ヘークを大幅に低減すること
ができる。
Effects of the Invention As described above, according to the present invention, cross 1 hake can be significantly reduced with an extremely simple and easy-to-implement configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における半導体装置の斜視図
、第2図は従来の半導体装置の斜視図である。 11・・・第1の導体配線、12・・第2の導体配線、
13シリコン基板、15・・第z3の導体配線代理人 
  森  本  義  弘 第1図 第2図
FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a perspective view of a conventional semiconductor device. 11...First conductor wiring, 12...Second conductor wiring,
13 silicon substrate, 15... z3 conductor wiring agent
Yoshihiro MorimotoFigure 1Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、隣接して位置する信号線用の第1及び第2の導体配
線間に、半導体基板と接続された第3の導体配線を配置
した半導体装置。
1. A semiconductor device in which a third conductor wiring connected to a semiconductor substrate is disposed between adjacent first and second conductor wirings for signal lines.
JP25107585A 1985-11-08 1985-11-08 Semiconductor device Pending JPS62111450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25107585A JPS62111450A (en) 1985-11-08 1985-11-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25107585A JPS62111450A (en) 1985-11-08 1985-11-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62111450A true JPS62111450A (en) 1987-05-22

Family

ID=17217259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25107585A Pending JPS62111450A (en) 1985-11-08 1985-11-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62111450A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0225156U (en) * 1988-08-05 1990-02-19
JPH0261052U (en) * 1988-10-28 1990-05-07

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092635A (en) * 1983-10-27 1985-05-24 Fujitsu Ltd Semiconductor device
JPS60214562A (en) * 1984-04-11 1985-10-26 Nec Corp Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6092635A (en) * 1983-10-27 1985-05-24 Fujitsu Ltd Semiconductor device
JPS60214562A (en) * 1984-04-11 1985-10-26 Nec Corp Semiconductor integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0225156U (en) * 1988-08-05 1990-02-19
JPH0261052U (en) * 1988-10-28 1990-05-07

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