JPS62121987A - Memory circuit - Google Patents

Abstract

PURPOSE:To speed up reading data out of a static type memory by employing a diode connection P-channel transistor as the load of a presense amplifier differential amplifier. CONSTITUTION:When a column signal from a terminal 11 comes to H at the time of reading, a transistor 18 is turned on to operate the presense amplifier differential amplifier formed with transistors 14 and 15. Storage contents in a selected memory cell 1 are read out through a main sense amplifier 23, etc. The diode connection transistors 21 and 22 are used as the load of the differential amplifier. The amplitude of the output of the presense amplifier is limited without suppressing a current gain, and the time necessary for inverting the output of the presense amplifier is shortened, whereby the reading time of the static type memory can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit having a static type configuration, and in particular to speeding up reading.

[Summary of the invention]

The present invention suppresses the amplitude of the output of the pre-sense amplifier by using a diode-connected P-channel MOS transistor as the load of the differential amplifier for the pre-sense amplifier in a memory circuit with a static type configuration.
It is designed to enable high-speed operation.

[Conventional technology]

FIG. 4 shows the configuration of the main parts of an example of a static RAM (Random Access Memory) using conventional MOS transistors.

The static type RAM shown in FIG. 4 has data lines 62 and 63 for writing and data lines 69 and 7 for reading.
0 and 0 separately.

In FIG. 4, 51 indicates a memory cell, and a plurality of memory cells 51 are two-dimensionally arranged in a matrix. Each memory cell 51 is composed of 79717071 circuits of MOS transistors whose inputs and outputs are cross-connected, and MOS transistors for gates that input and output data are connected to both ends of this flip-flop circuit. ing.

Memory cells 51 arranged in the row direction share a common word *52
connected to. This word line 52 is connected to an X decoder (not shown), and a row address is specified.
One word line 52 is designated. And this word line 52
The MOS transistor for the gate of the memory cell 51 in the row corresponding to is turned on.

The memory cells 51 arranged in the column direction are connected to a common pair of bit lines 53 and 54.

One ends of the bit line 53 and bit line 54 are connected to the drains of a load MOS transistor 55 and a MOS transistor 56, respectively. As the MOS transistors 55 and 56, P-channel transistors are used. The sources of the MOS transistor 55 and the MOS transistor 56 are connected to a power supply terminal 57 of a power supply voltage .fltl (for example, 5 V). The gates of the MOS transistor 55 and the MOS transistor 56 are commonly connected, and this connection point is grounded.

The other ends of the bit line 53 and the bit line 54 are connected to a switching MO5I transistor 58 and a MOS transistor 59.
are connected to the drains of each. MOS transistor 58
and MOS) As the transistor 59, an N-channel transistor is used. MOS transistor 58 and MO3
The source of the I-transistor 59 is the data line 6 for writing.
2 and data line 63, respectively. The gates of the MOS transistor 58 and MO3I-transistor 59 are commonly connected, and the column signal input terminal 6 is connected from this connection point.
1 is derived.

During writing, the data line 62 and data line 63 for writing are used. A column signal is supplied to the column signal input terminal 61 from a Y decoder (not shown). When the column signal becomes high level, the MOS transistor 58 and the MOS transistor 59 are turned on. As a result, a column address is designated and one memory cell 51 is selected. Data transmitted through the data line 62 and the data line 63 is written into the selected memory cell 51.

The gates of a MOS transistor 4 and a MOS transistor 5 constituting a pre-sense amplifier are connected to the bit line 53 and the bit line 54, respectively. As the MOS transistor 64 and the MOS transistor 5, N-channel ones are used.The sources of the MOS transistor 64 and the MOS transistor 5 are connected in common, and this connection point serves as the MOS transistor 6 which operates as a constant current source. connected to the drain of the MOS transistor 6
4 and the MOS transistor input taro 5 constitute a differential amplifier. MOS transistor 66 is driven by DC power supply 67. 0 where the source of MOS) transistor 6 is grounded via switching MO5) transistor 8
The gate of M0S transistor 68 is connected to column signal input terminal 61.

The drains of the MOS) transistor 5 and the MOS) transistor 4 are connected to a data line 69 and a data line 70 for reading.
are connected to each. The drains of the loads MOS) Langisthu 1 and MOS) Langisthu 2 are connected to the data line 69 and the data line 70, respectively. As the MOS transistor 1 and the MOS transistor 72, P-channel transistors are used. MOS) Langistav 1 and M
OS) The source of Langstaff 2 is connected to power supply terminal 57. MOS) The gates of the transistor 1 and the MOS transistor 72 are commonly connected to each other.

This connection point is connected to the drain of the MOS Langistuf 1, and a current mirror circuit is constituted by the MOS Langisturf 1 and the MOS transistor 72.

At the time of reading, a data line 69 and a data line 70 for reading are used. When the column signal supplied to the column signal input terminal 61 becomes high level, the MOS I-transistor 8 turns on, and the MOS transistors 64 and M
A pre-sense amplifier consisting of O5I-Ranjistaro 5 operates. As a result, one memory cell 51 is designated, and the data stored in this memory cell 51 is
It is supplied to the gates of the OS) transistor 64 and the MOS transistor 5. MOS) Langista 1 and 72 are MOS) Langista 4 which constitutes a pre-sense amplifier.
and MOS) operates as a current mirror load circuit for the transistor 5.

That is, when a high level is supplied to the gate of the MOS transistor 5 and a low level is supplied to the gate of the MOS transistor 64, the MOS transistor 65 is turned on and the MOS transistor 64 is turned off. For this reason, M.O.
S) Current flows through the MOS transistor 5 through the transistor 1.

MOS) Langistav 1 and MOS) Langistav 2 constitute a current mirror circuit, so at this time, M
Equal currents flow through the O3t-rangestaff 1 and the MOS transistor 72. The current flowing through MOS) Ranjistaph 2 is as follows: Since MOS) Ranjistaph 4 is off,
This flows into the stray capacitance of the data line 70, and as a result, the voltage of the data line 70 increases.

When a high level is supplied to the gate of MOS) transistor 4 and a low level is supplied to the gate of MOS) transistor 5, MOS) transistor 4 turns on and the MOS
) Rangistaro 5 turns off. For this reason, the current flowing through the MO3I-Langistaft 1 decreases, and the current flowing through the MOS Langistav 2 decreases. The charge stored in the capacitance of the data line 70 is discharged via the MOS transistor 4, and the voltage of the data line 70 decreases.

One ends of the data line 69 and the data line 70 are connected to a non-inverting input terminal and an inverting input terminal of the main sense amplifier 73,
The output of a pre-sense amplifier consisting of a MOS transistor 4 and a MOS transistor 65 is supplied to a main sense amplifier 73. The output of main sense amplifier 73 is supplied to data output terminal 75 via inverter amplifier 74.

[Problem that the invention seeks to solve]

In this way, in the conventional static RAM equipped with data lines 62, 63 for writing and data lines 69, 70 for reading, read data is supplied to a pre-sense amplifier consisting of MOS transistors 4 and 65; The configuration is such that the output of the pre-sense amplifier is supplied to the main sense amplifier 73 and the output data is taken out. and,
As a load circuit for this pre-sense amplifier, a current mirror circuit consisting of MOS) Langisthus 1 and 72 is used. Therefore, there is a problem in that the amplitude of the output voltage of the pre-sense amplifier becomes large and the time required to invert the read data becomes long.

That is, the data lines 69 and 70 have stray capacitance, and the output of the pre-sense amplifier is obtained by charging and discharging this capacitance, as described above. Therefore, the output voltage of the pre-sense amplifier increases or decreases with the charging/discharging time of this capacitor, and has a large amplitude. This amplitude is the load MOS)
Increase the size of Rungistaft 1゜72 (and load MOS
Even if the resistance ros of the transistor OFF 1.72 is made moderately small, the amplitude at the bit line 53.54 (1, OV p −
p) It will be equivalent to or more than that.

In order to suppress the amplitude of the pre-sense amplifier, if the conductance gm of the MOS transistors 4 and 65 of the pre-sense amplifier is made small, the current gain will not increase and the charging/discharging current will not be sufficient for the stray capacitance of the data lines 69 and 70. can no longer flow. Therefore, although the amplitude of the output of the pre-sense amplifier becomes smaller, the inversion time never becomes faster.

When accessing the memory cell 1 in the row direction, an internal pulse is generated by detecting the address transition, and the bit lines 53 and 54 are balanced by this pulse.
Equalization circuits are often provided to enable high-speed operation; however, on the column side, accesses in the column direction (column direction) are accessed in the row direction, and data output to the bit line is selected. Therefore, an equalization circuit is not provided because the access time is essentially faster due to the access time in the row direction, and providing an equalization circuit would lead to an increase in chip area and power consumption.

Therefore, an object of the present invention is to provide a memory circuit that can suppress the amplitude of the output of a pre-sense amplifier without lowering the current gain and shorten the inversion time without using an equalization circuit.

[Means for solving problems]

This invention connects a differential amplifier for a pre-sense amplifier to a bit line pair, controls the switching of this differential amplifier for a pre-sense amplifier by a column signal, and uses a diode-connected P as a load of the differential amplifier for a pre-sense amplifier. This is a memory circuit characterized in that a channel MO3I-transistor is used and the output of a differential amplifier for a pre-sense amplifier is supplied to a main sense amplifier.

[Effect]

Diode-connected P-channel MOS transistors 21 and 22 are used as a load circuit for a pre-sense amplifier consisting of MOS transistors 14 and 15. Since the load MOS transistors 21 and 22 are diode-connected in this way, the amplitude of the output of the pre-sense amplifier is limited. This shortens the inversion time of the output of the pre-sense amplifier, enabling high-speed operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, l indicates a memory cell, and a plurality of memory cells 1 are two-dimensionally arranged in a matrix. Each memory cell 1 has mutual input and output.

It consists of a flip-flop circuit of MOS transistors connected across the board, and MOS transistors for gates for inputting and outputting data are connected to both ends of the flip-flop circuit.

Memory cells 1 arranged in the row direction are connected to a common word line 2. This word line 2 is an X decoder (not shown)
When a row address is specified and one word vA2 is specified, the MOS transistor for the gate of the memory cell 1 in the row corresponding to this word line 2 is turned on.

Memory cells 1 arranged in the column direction are connected to a common pair of bit lines 3 and 4. One end of bit NlA3 and pin) *4 is load MOS) transistor 5 and MO
They are connected to the drains of the S transistors 6, respectively. M.O.S.
) P-channel transistors are used as transistors 5 and 6. The source of the MOS transistor 5 and MOS) transistor is connected to the power supply terminal 7 of the power supply voltage Van (for example, 5V).
The gates of the S transistors 6 are commonly connected, and this connection point is grounded.

The other end of bit ts3 and bit line 4 is connected to switching M
They are connected to the drains of the OS transistor 8 and the MOS transistor 9, respectively. MOS) transistor 8 and MOS
) As the transistor 9, an N-channel transistor is used. MOS) transistor 8 and MOS) transistor 9
The sources are data lines 12 and 13 for writing.
are connected to each. MO5I - transistor 8 and MOS
) The gates of the transistors 9 are commonly connected, and a column signal input terminal 11 is led out from this connection point.

During writing, the data line 12 and data line 13 for writing are used. A column signal is supplied to the column signal input terminal 11 from a Y decoder (not shown). When the column signal becomes high level, the MOS transistor 8 and the MO3I transistor 9 are turned on. This specifies the column address and one memory cell 1
is selected. Data line 1 to selected memory cell 1
2 and the data transmitted via data NlA13 are written.

The gates of a MOS transistor 14 and a MOS transistor 15 constituting a pre-sense amplifier are connected to the bit line 3 and the bit tlA4, respectively.

As the MOS transistor 14 and the MOS transistor 15, N-channel transistors are used.

The sources of the MOS) transistor 14 and the MOS) transistor 15 are commonly connected, and this connection point is connected to the drain of the MO5I transistor 16, which operates as a constant current source, and the MOS transistor 14 and the MOS) transistor 15 are connected to each other. The amplifier is configured. MOS transistor 16 is driven by DC power supply 17 . M.O.S.
The source of transistor 16 is grounded via switching MOS transistor 18. MOS) transistor 1
8 is connected to the column signal input terminal 11.

The drains of MOS) transistor 16 and MOS) transistor 14 are connected to read data line 19 and data 'a2.
0 respectively. The data line 19 and the data line 20 are connected to diode-connected MOS transistors 21 and 22.
As the 0M0S transistor 21 and the MOS1-transistor 22 whose respective gates and drains are connected,
A P channel is used. The sources of MOS) transistor 21 and MOS) transistor 22 are connected to power supply terminal 7.
connected to.

At the time of reading, a data line 19 and a data line 20 for reading are used. When the column signal supplied to the column signal input terminal 11 becomes high level, the MOS transistor 18 turns on, and the MOS transistor 14 and MO
A pre-sense amplifier consisting of an S transistor 15 operates. As a result, one memory cell 1 is designated, and the data stored in this memory cell 1 is transferred to the bit line 3.
and is output via the bit line 4, and this data is output to the MOS
It is supplied to the gate of transistor 14 and transistor 15 (MOS). Diode-connected MOS transistors 21 and 22 constitute a pre-sense amplifier)
It operates as a load for transistors 14 and 15.

Now, suppose that the focus line 3 is at a low level, bit '41A4 is at a high level, a high level is supplied to the gate of the MOS transistor 15, and a low level is supplied to the gate of the MOS transistor 14. The MOS transistor 14 is turned on and the MOS transistor 14 is turned off.

For this reason, the diode-connected MOS) transistor 2
A current flows through the capacitance of the data line 20 due to the current flowing through the data line 20, and the voltage of the data line 20 increases.

A diode is a non-linear element as shown in FIG.

Therefore, the voltage of data [20] at this time is the power supply voltage ■
If DD is, for example, 5■, it is limited to, for example, 4.2V.

The data on bit lines 3 and 4 are inverted, a low level is supplied to the gate of MOS transistor 15, and MOS1-
When a high level is supplied to the gate of transistor 14,
The MOS) transistor 14 is turned on, and the MOS) transistor 15 is turned off. Therefore, the charge stored in the capacitance of the data line 2o is discharged, and the voltage of the data line 20 decreases.

In this embodiment, a diode-connected MOS transistor 21 is used as the load of the pre-sense amplifier.
and 22 are used. Therefore, the amplitude of the pre-sense amplifier is limited without suppressing the current gain, and the third
As shown by the solid line in Figure B, the high level of the output of the pre-sense amplifier is, for example, 4.2V, and the low level is, for example, 3.8V.
v.

As is clear from FIG. 3, by limiting the amplitude of the pre-sense amplifier in this way, the inversion time is shortened and high-speed operation is possible. In other words, with respect to the bit line output waveform shown in FIG. 3A, the broken line in FIG. 3B shows the output waveform of the pre-sense amplifier without amplitude limitation, and the solid line in FIG. 2 shows the output waveform of the pre-sense amplifier when the present invention is applied and amplitude limitation is performed. If amplitude limitation is not performed, for the bit line data transition time T01 and Toz,
The output data of the pre-sense amplifier is the time Tel and T'
Invert with zz. When the amplitude is limited, the output data of the pre-sense amplifier is at times T, 1 and T'+ for the bit line data transition time T (11 and Tl12).
Invert with z. The time required for inversion when amplitude limitation is applied (To, ~T, To t = T + t) is the time required for inversion when amplitude limitation is not performed (T01
~T, , T, , ~T z t ).

This enables high-speed operation.

〔Effect of the invention〕

According to the invention, the amplitude of the output of the Brisense amplifier is limited without reducing the current gain.

Therefore, the time required to invert the output of the brisense amplifier is shortened, and high-speed read operation is possible.

[Brief explanation of drawings]

Figure 1 is a connection diagram of an embodiment of this invention, Figure 2 is a graph used to explain an embodiment of this invention, Figure 3 is a waveform diagram used to explain an embodiment of this invention, and Figure 4. 1 is a close-up diagram of an example of a conventional memory circuit. Explanation of main symbols in the drawings 1: Memory cell, 3.4j bit line. t4. ts: MOS transistor constituting the Brisense amplifier, 21.22: Load MOS transistor,
23: Main sense amplifier. Fig. 1 γioto PO7~kai 1 Fig. 2 Ieko 1st item Fig. 3 (Shiba, Kasai φj Fig. 4

Claims (1)

[Claims] A differential amplifier for the pre-sense amplifier is connected to the bit line pair, switching of the differential amplifier for the pre-sense amplifier is controlled by a column signal, and a diode-connected P-channel MOS transistor is used as a load of the differential amplifier for the pre-sense amplifier. A memory circuit characterized in that the output of the differential amplifier for the pre-sense amplifier is supplied to the main sense amplifier.