JPS62122169A - Manufacturing method for semiconductor devices - Google Patents

Abstract

PURPOSE:To improve the performances by forming an emitter region and a graft base subject to self-alignment by a method wherein impurity in high concentration is implanted in the surface of Si substrate to form the emitter and a base for diffusing the impurity in emitter and collector regions through the intermediary of a poly-Si film. CONSTITUTION:An emitter region (true base region) 24 and an oxide film on a collector region (CN) are removed to form a poly-Si film 25 on overall surface. This poly-Si film 25 implanted with As (arsenic) ion in high concentration. Next As contained in the poly-Si film 25 is diffused in an Si substrate by annealing process to form an emitter N<+> type layer 26 and a collector contact N<+> type layer 27. Later (or before the annealing process) any needles parts of poly-Si are removed by photoetching process to leave them as the emitter poly-Si electrode 25 and a collector poly-Si electrode 25b. Through these procedures, after performing the masking process for the first selective oxidation of the poly-Si film, the masking process with high precision can be omitted to form the emitter base subject to self-alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device having a graft (outer) pace by self-alignment (self-alignment technology), and primarily relates to craft-based transistor manufacturing technology.

[Background technology]

The performance of high-speed bipolar transistors is determined by the cutoff frequency (fT
) and pace resistance (rbb'). high fT
It is effective to reduce the parasitic capacitance by forming the junction shallowly and by miniaturizing the transistor to obtain K, but rbb' tends to increase accordingly, and it is difficult to reduce the parasitic capacitance by simply making the standard transistor smaller. Therefore, sufficient performance cannot be obtained. Therefore, a graft base transistor has been proposed in which the base and emitter are formed in a self-aligned manner using polycrystalline (poly)silicon, and has a narrow base width, low concentration intrinsic base, and deep, high concentration craft space. Various manufacturing processes for this purpose have been reported. “Very LSI Device Handbook JP68-” published by Science Forum Co., Ltd. November 18, 1981
For example, according to a graft base formation method conventionally known as a selective oxidation method, after forming a shallow low concentration p-type layer for an intrinsic paste on the surface of a (lln-1118i substrate), (2) silicon・Night Ride (S is N
4) Diffuse B (boron) using the M mask to form a deep, high concentration p+ type layer that will become a kraft paste, and (3) then oxidize it. The surface part has a thick oxide film,
(Remove the 41SiN film, and form an n-type layer by diffusing the emitter using the above thick oxide film as a mask. (5) After that, deposit poly-Si on the entire surface, pattern it using photoresist, and form a poly-Si emitter. According to this method, since the poly-Si electrode does not rely on self-alignment lines, a large area is taken up by patterning, and the craft paste p-type layer and emitter B+ are formed on the Si surface.
There is a problem in that the emitter-base breakdown voltage decreases due to the close proximity of the mold layer.

According to the poly-Si stack utilization method, which is another conventionally known graft-based formation method, (after forming an intrinsic paste p-type layer on the surface of the 11Si substrate, emitter diffusion is performed through a window in the oxide film, forming a shallow n-type layer,
(2) form a poly-Si emitter electrode that is ohmically connected to the n-type layer; (3) use the poly-Si electrode as a mask to form a B(
Graft-based pNNs are formed by injecting boron (boron) into Si.

In this method as well, since the poly-Si electrode does not depend on the self-line, mask alignment margin is required to reduce the breakdown voltage between the craft paste and the emitter. There is a problem in that the parasitic capacitance increases due to the overlap.

As a further improved method of the above method, there is a method that uses nitride and uses selective oxidation and poly-Si in combination.

The process will be described below with reference to FIGS. 10 to 16.

(1) On the surface of the n-type Si substrate 1, p-
A mold /i12 is formed, and a thin S t Ot is formed on the surface of the mold /i12.
Film 3 A first Si, N4 film 4 is formed, and a portion that is to become an emitter is removed, while the rest is removed. Then po IJ on the entire surface
A Si film 5 is formed, a second Si, N, film 6 is formed on the surface, and the first 5i3N4 film 4 is formed by using a step formed by the first Si3N film or by using a photoresist. (2) Selectively oxidize the poly-Si film using the second Si and Nl2 as a mask to form an oxide film 7. (Figure 11).

(3) Remove the second Si3N4 film 6 and add a high concentration of B+(
Boron) is ion-implanted and diffused to form a graft base forming layer 8 on the surface of the substrate (FIG. 12).

(4) Remove oxide film 7 (FIG. 13).

(5) Bo IJSi film 5 and exposed Si substrate (p-
Type Iψ) oxidize the surface to form S t 02 film 9 (
Figure 14).

(6) First Si3N, film 4 and thin Si0 below
2 film 3 is removed (FIG. 15).

A second poly-Si film 10 is formed on the entire surface, and AS ions are implanted thereon to form an n-type layer 11 that will become an emitter on the substrate surface using the Si film as a mask.

According to the above method, the distance d between the emitter region 11 and the graft base p-type layer 8 can be as small as about 1 μm, and Rbb
However, it is not preferable that the number of photoresist steps is small (two in each case).

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned problems. Therefore, an object of the present invention is to obtain a high-performance semiconductor device by forming an emitter and a graft base using self-alignment.

[Summary of the invention]

A brief overview of typical inventions disclosed in the present invention is as follows.

That is, a first poly-Si film is formed on the surface of a Si semiconductor substrate, and a first poly-Si film on a region to be connected to the emitter and collector is selectively oxidized to form an oxide. A high concentration impurity for base diffusion is introduced into the first IJ Si film, and then the above oxide is removed to expose a part of the Si substrate, and the surface of the Si substrate in the part that is to become the emitter is A low concentration impurity for intrinsic base diffusion is introduced into the substrate, and then a graft base is formed on the surface of the Si substrate by impurity diffusion from the first poly-Si film by annealing, and at the same time, an intrinsic base is formed by diffusion of the low concentration impurity. . After that, a second poly-Si film is formed on the entire surface, and high-concentration impurities for emitter and collector diffusion are introduced into the Si substrate surface through this second poly-Si film to form an emitter and a base. As a result, the emitter and base can be formed in a self-aligned manner, the craft base region can be reduced, the base resistance and the collector-base capacitance can be reduced, and a high-performance semiconductor device can be provided.

〔Example〕

FIGS. 1 to 8 show an embodiment of the present invention, and are cross-sectional views of a manufacturing process of a transistor having a graft base. Each step will be explained in detail below.

(11 Prepare a semiconductor substrate, for example, a p-type St substrate (substrate) 12 on which an n+-type buried layer 13 is partially buried and an n-type 5iJfi 14 is epitaxially grown. This n-type Si layer 5i formed on the surface of 14
A thick oxide film 16 for isolation is used to selectively oxidize the surface of the n-type Si layer using a mask 15 of lN, (silicone idride), etc.
Highly concentrated P (IJ) is introduced and diffused into the Si layer (14) of one isolated island region by ion implantation, and the collector is taken out and the n+ type m (CN layer) 17 is converted into an n+ type buried layer. 13 (FIG. 1).

+21 fi [Si was deposited to form a poly-Si film 18 on the entire surface, and S! sN4 membrane 1
Poly-Si on the emitter/collector area using 9 as a mask.
The film 18 is selectively oxidized to form an oxide film 20 (FIG. 2).

Next, by implanting highly concentrated MB'' (boron) ions into the entire surface, B is doped in the poly-Si film 1g.

At this time, the ion implantation energy was controlled to prevent crystal defects from occurring on the surface of the Si substrate (141), and Rp
so that it remains in polySi, [18.

(3) Next, the Si3N film 19 is removed and the selectively oxidized portion (8102) 20 is etched to expose the emitter region α and collector region aη of the Si substrate (Fig. 3).
.

(4) A thin 5102 film 21 is formed by thermally oxidizing the surface of the poly-Si film I8, or a 5in2 film (21) (hereinafter referred to as HLD film) is deposited at high temperature and low pressure using the CVD method (chemical deposition method). A mask 2 of a photoresist film with an opening only on the base region.
2 is formed, low-concentration B is ion-implanted into the region 14 that is to become the intrinsic base (the region immediately below the emitter region) (FIG. 4).

(5) After this, annealing is performed and B+ in poly-Si is
Diffuse onto the substrate surface to graft base p” type 1?123
At the same time, B implanted into a part of the surface is diffused to form an intrinsic base region 24.

In this case, as shown in FIG. 5, the intrinsic base region 24 is formed shallowly, and the graft base p is sandwiched therebetween.
The + type layer 23 is formed deep.

(6) The oxide film on the emitter region (intrinsic base region) 24 and collector region (CN) is removed by etching, and the second
25 is formed. Highly concentrated AS (arsenic) ions are implanted into this second poly-Si film 25 (FIG. 6).

(7) By performing annealing and diffusing As in the second poly-Si film 25 into the Si substrate, the emitter n”W712
6 and a collector contact r1+ type layer 27 are formed. After this (possibly even before annealing), the unfinished portion of the poly-Si is removed by photoetching, and the emitter poly-Si electrode 25a is
and left as collector poly-Si electrode 25b (Fig. 7)
.

(8) Forming SiQ film 28 on the entire surface by CVD method,
Through-hole etching is performed to expose a portion of the IJSi film of each electrode. Note that in the first poly-Si film 18 in contact with the graft base p-type layer 23, a part of the oxide film 21 on the surface is removed before or after through-hole etching. After that, AJt electrodes (wirings) 29 are formed by evaporating or sputtering A[, wiring patterning and etching with photoresist, and connecting to each poly-Si electrode through through holes.
Figure 8).

In this way, a semiconductor device having a graft base and a poly-Si electrode is completed. FIG. 9 is a plan view showing the electrode arrangement corresponding to FIG. 8.

〔Effect of the invention〕

According to the present invention described in the above embodiments, the following advantages can be obtained.

(1) After the masking process is performed for the first selective oxidation of the poly-Si film, a highly accurate masking process is not necessary, and the emitter Φ pace is formed in a self-aligned manner.

(2) The graft base area is reduced compared to the above (IIK), the base resistance rbb' can be made extremely small, and the capacitance between the collector and the base can be made small.

(3) A high-speed, high cut-off number wave frequency transistor can be provided without significantly increasing the number of steps.

(4) In step (4), when the SiQ film 21 is formed by oxidizing the poly-Si film 18, as shown in FIG. The film thickness t1 is larger than the oxide film thickness t2 on the surface of the Si substrate 14, which is advantageous for selectively etching the oxide film on the surface of the Si substrate by simply pickling.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above examples and can be modified to a certain extent without departing from the gist thereof. Mona...

For example, in the process of Example 1, if step (41) is abolished and the next step (5) is performed without forming the intrinsic paste p- type layer as shown in FIG. A lateral pnp transistor using the mold dove 25 as an emitter and collector can be formed in a self-aligned manner.Alternatively, in the process of the first embodiment, step (7)
), and as shown in FIG.
It can be used as a resistor made of p-type 1if24 with electrodes.

[Application field]

The present invention can be applied to bipolar ICs in general, and is particularly effective when applied to high-speed pibolar mesoris and logic circuits and high fT semiconductor devices.

[Brief explanation of drawings]

FIGS. 1 to 8 are cross-sectional views of a manufacturing process of a graft-based transistor showing an embodiment of the present invention. FIG. 9 is a plan view corresponding to FIG. 8. FIGS. 10 to 16 are cross-sectional views of a conventional graft-based transistor manufacturing process. FIGS. 17 to 19 are sectional views showing other embodiments of the present invention. 12...p-type Si substrate, 13...n-type buried layer,
14...Epitaxial n-type SiM, 15...S
i, N, film, 16... isolation oxide film, 17
...Collector extraction n-type 1.18...Poly S1 film,
19...Si3N, film, 20... Oxide film, 21...
・Thin oxide film, 22... Mask, 23... Graft base p+ type island, 24... Intrinsic base p- type tank, 2
5... Poly-Si film, 26... Emitter n-type layer, 2
7...Collector Contact nfian, 28...C
VD・S i02 film, 29...AI electrode. Figure 1/, j Figure 2 Figure 3 Figure 4 Figure 5 Figure 7 Figure 8 Figure 14 Figure 15 Figure 16 Figure 17/4 1). 26 Showa Kiri year 5th day

Claims (1)

[Scope of Claims] 1. A first polycrystalline semiconductor film is formed on one main surface of a semiconductor substrate, and a portion of the first polycrystalline semiconductor film is made of a selective oxide with a high concentration. After introducing an impurity and then introducing a low concentration impurity of the same conductivity type as the above impurity into the surface of the semiconductor substrate through a part of the portion from which the selective oxide has been removed, the above impurity is introduced into the above substrate by an annealing treatment. A second polycrystalline semiconductor film is formed by diffusing to form an intrinsic base and a graft base sandwiching this, and then a second polycrystalline semiconductor film is formed to fill the portion from which the selective oxide has been removed, and this second polycrystalline semiconductor film is 1. A method of manufacturing a semiconductor device, comprising forming an emitter or a collector by diffusing impurities introduced into the base into the base. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film is formed on the surface of the polycrystalline semiconductor film after the selective oxide is removed.