JPS621226B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, frequency adjustment of a quartz watch was performed using a trimmer capacitor. However, the capacitance value of the trimmer capacitor shifts due to aging, so it is not desirable to use it in high-precision crystal watches. Therefore, the built-in capacitance value of the oscillator is configured to be switchable to obtain multiple oscillation frequencies, and the average frequency is adjusted by controlling the proportion of time for multiple oscillation conditions using an external input code. A method has been proposed. However, if the timing to switch the oscillation conditions coincides with the motor drive timing,
A problem arises in that the oscillator becomes unstable due to the influence of battery voltage fluctuations.

The present invention has been made to eliminate the above-mentioned problems by fixing the oscillation conditions of the oscillator to the most stable state while the motor is being driven.

FIG. 1 is a block diagram of an embodiment of an electronic timepiece according to the present invention.

In FIG. 1, 2 is a crystal oscillation circuit, and the reference signal output from this circuit is divided by a frequency dividing circuit 4 to 1
The Hz signal is sent to the motor drive circuit 6. The drive circuit 6 drives a motor 8, and the motor 8 operates the pointer type display device 10.

The oscillation circuit 2 has an electronic switch 12, by which the input capacitance can be changed. Figure 2 shows the frequency of crystal oscillation circuit 2.
This is a diagram showing temperature characteristics, but when switch 12 is
When turned ON, the input capacitance increases, so see Figure 2.
It oscillates at a relatively low frequency shown in ₁ , and the switch 1
When 2 is turned OFF, the input capacitance becomes smaller, so oscillation occurs at a relatively high frequency as shown in _FIG . Therefore, by changing the ratio of the time when the switch 12 is turned on and the time when it is turned off, a frequency between ₁ and ₂ can be obtained. In this embodiment, initial frequency adjustment and temperature compensation of the crystal oscillation circuit 2 are performed by controlling the switch 12.

The switch 12 is controlled by a switch control circuit 14.
Controlled ON and OFF. Switch control circuit 14
Turn on switch 12 at the beginning of each unit time or
OFF, and the state is canceled by the coincidence signal from the coincidence detection circuit 16. The coincidence detection circuit 16 connects the output group of the selector 20 sent to the line 18 and the frequency divider circuit 4.
Compare the outputs of and output a match signal if they match. Therefore, the signal on line 18 causes switch 12 to
The ON/OFF time ratio changes, and as a result, the average frequency of the reference signal output from the crystal oscillation circuit 2 changes.

A temperature-sensitive oscillator 22 has a ring oscillator configuration whose cycle is determined by a temperature-sensitive resistor and a capacitance. The oscillation control circuit 20 controls the oscillation of the temperature-sensitive oscillator 22,
This is a circuit that controls stopping, and the temperature-sensitive oscillator 22 is activated intermittently.
Outputs the oscillation start command to. The reason for intermittent oscillation is mainly to reduce the average power consumption of the temperature-sensitive oscillator 22. The variable frequency divider circuit 24 outputs an output signal when the number of pulse signals set by the frequency division ratio setting means 26 is sent from the temperature-sensitive oscillator, and in response to the output signal, the oscillation control circuit 20 operates the temperature-sensitive oscillator. 22
to stop. The frequency division ratio setting means 26 is provided to absorb variations in the oscillation frequency of the temperature-sensitive oscillator 22, and the frequency division ratio of the variable frequency division circuit 24 is changed by the means 26, and the frequency division ratio of the variable frequency division circuit 24 is changed. The period-temperature characteristics of the output signal are adjusted to a constant value.
Since 22 is a temperature-sensitive oscillator, the period of the output signal of the variable frequency dividing circuit 24, that is, the time from when the temperature-sensitive oscillator 22 starts oscillating until it outputs a desired number of pulse signals, changes depending on the temperature. Therefore, the temperature can be determined from the time.

The ROM 28 stores data for temperature compensation. This data is used to change the ratio between the ON time and OFF time of the switch 12 in response to temperature changes, and is required by the coincidence detection circuit in order to obtain the desired ratio.
The output data of ROM 22 is read into latch 30. The output of the frequency dividing circuit 4 is connected to the address signal end of the ROM 28. Since the temperature-sensitive oscillator 22 starts oscillating in response to the output of the frequency dividing circuit 4,
At the start of oscillation, the internal state of the frequency divider circuit 4 is constant. Therefore, after a certain period of time has passed since the temperature-sensitive oscillator 22 starts oscillating, the ROM 28 will have been designated with a certain address. The latch 30 responds to the output signal of the variable frequency divider circuit 24 to
Read the output data of 8. As mentioned above, the time from the start of oscillation of the temperature-sensitive oscillator 22 until the output of the variable frequency divider circuit 24 changes depending on the temperature.
Latch 30 will read data stored at different addresses in ROM 28 depending on the temperature. Therefore, by writing the temperature compensation data necessary for each temperature into each address of the ROM, the temperature compensation data will be latched every time the temperature-sensitive oscillator 22 oscillates.
Reads to 0. Note that the φ signal sent to the ROM 28 is for reducing the power consumption of the ROM, and the ROM 28 is sent only while the φ signal is present, that is, only when reading ROM data into the latch 30.
is in an active state. The temperature compensation data read into the latch 30 is sent to the coincidence detection circuit 16 via the selector 21.

FIG. 3 shows the frequency-temperature characteristics when temperature compensation is performed in this manner. In the characteristics shown in FIG. 3, the amplitude of the vertical axis can be made smaller as the resolution of the temperature to be detected is increased and the resolution of the temperature compensation data sent to the coincidence detection circuit 16 is increased. In order to increase the resolution of the detected temperature, it is necessary to increase the number of words in the ROM 28, and in order to increase the resolution of temperature compensation data, it is necessary to increase the number of bits constituting a word.

Compensation reaches its limit beyond the temperature at which curve ₂ in FIG. 3 coincides with the desired frequency. In other words, when t is less than ₁ and more than t ₂ in Figure 3, it becomes _1.
With the combination of (2) and ₍₂₎ , it becomes impossible to create the desired frequency. In such a case, switch 12 should be turned on to reduce the error from the desired frequency.
Fix it to OFF and set the output frequency of crystal oscillator circuit 2.
It is desirable to fix the characteristics to ₂ . A compensation limit detection circuit 32 is provided for this purpose. The compensation limit detection circuit 32 detects, based on the signal from the frequency dividing circuit 4, that the time from when the temperature-sensitive oscillator 22 starts oscillating to when the variable frequency dividing circuit 24 outputs an output signal exceeds a certain range. . The detected signal is sent to the switch control circuit 14, and the switch 12 is turned off in response to the detected signal.

The code output means 34 is provided to adjust the initial value of the oscillation frequency of the crystal oscillation circuit 2. The signal of the code output means 34 is converted into a desired signal by the decoder 36, and the match is detected via the selector 20. The signal is sent to circuit 16. Therefore, the average oscillation frequency of the crystal oscillation circuit 2 can be controlled by the signal from the code output means 34.

The selector 21 selectively sends the temperature compensation data and initial value adjustment data to the coincidence detection circuit 16 in response to the periodic signal from the frequency dividing circuit 4. Shown in Figures 2 and 3
The frequency difference between ₁ and ₂ is 2△, and the duty cycle of the periodic signal applied to the selector 21 is 50%.
If so, both temperature compensation and initial value frequency adjustment can be adjusted by Δ.

4A and 4B are circuit diagrams of an embodiment of an electronic timepiece according to the present invention, showing circuit parts that can be integrated within the block 3. FIG. Note that blocks corresponding to those in FIG. 1 are given the same numbers.

The reference signal output from the crystal oscillation circuit 2 is input to a 15-stage frequency divider via an inverter 40 for waveform shaping, and a 1 Hz signal is obtained from the final stage frequency divider 42. The output of the fifth stage frequency divider 44 is taken out from the integrated circuit as an FC terminal, and is used as a fast-forward signal input terminal for checking the oscillation frequency and circuit function. A data type flip-flop (hereinafter abbreviated as DFF) 46 is provided to create the time width of a signal that drives the motor, and the output of the DFF 46 is sent to a frequency divider 42.
Since the output rises at the same time as the output falls and is reset in accordance with the output of the gate 48, the signal has a period of 1 second and a pulse width of approximately 5.9 _msec . DFF50 is motor drive timing and oscillation circuit switch 1
This was provided to ensure that the switching timings of the two do not match, and the output of the DFF46 is set to 512Hz.
The phase is delayed by rereading the signal.
The output of DFF50 is the motor drive circuit block 6.
As a result, drive pulses are output alternately from the OUT1 and OUT2 terminals.

22 is a temperature-sensitive oscillator and inverters 52, 54,
56, 58, 60 NAND gate 62 resistance R ₁ ,
It includes a multivibrator consisting of R ₂ , capacitors C ₁ and C ₂ and a gate 66 switch 64. The oscillation frequency of the multivibrator is determined by the time constants of R ₁ , R ₂ , C ₁ , and C ₂ . If R ₁ and R ₂ are diffused resistors and C ₁ and C ₂ are gate capacitors, both can be integrated. Since the temperature coefficient of the diffused resistor is approximately 0.7% per 1°C, which is sufficiently large compared to the gate capacitance, the temperature characteristic of the period of the multivibrator is approximately equal to the temperature characteristic of the diffused resistor.
NAND gate 62 oscillates a multivibrator,
The multivibrator starts oscillating when the output of the gate 66, which is input to the gate 62 as a stop control gate, becomes H, and stops oscillating when it becomes L. The switch 64 is provided to adjust the oscillation frequency of the multivibrator.
When turned on, resistor _R2 is shorted. If R ₁ and R ₂ are set to approximately equal values, the oscillation frequency can be approximately doubled by shorting the switch 64. Switch 64 is controlled by a signal applied to terminal _S9 . Note that the input circuit 68 is composed of a circuit shown in FIG. Terminal C is the multivibrator frequency check and variable frequency divider circuit 24.
This is an input/output terminal for checking the operation of the device.

The oscillation control circuit 20 is a circuit for causing the temperature-sensitive oscillator 20 to oscillate intermittently, and synthesizes the signals from the frequency divider circuit 4 at a gate 70, and divides the synthesized signal by a seven-stage frequency divider 72 to generate 128 Create a signal with a period of seconds.
The DFF 74 is triggered by the falling edge of the signal and outputs an oscillation start command signal for the temperature-sensitive oscillator. The signal is applied to one input of the gate 66, and as a result, the output of the gate 66 becomes H, so that the temperature sensitive oscillator 22
starts oscillating. When the temperature-sensitive oscillator 22 outputs a predetermined number of pulse signals, the variable frequency divider circuit block 2
A signal is output from the gate 82 of No. 4, and the signal is
Applied to the reset end of DFF 74 via OR gate 76. As a result, the output of DFF becomes H and the output of gate 66 becomes L, so temperature-sensitive oscillator 22
stops oscillation. In this way, the temperature-sensitive oscillator 2
2 oscillates every 128 seconds and automatically stops after outputting a predetermined number of pulse signals. Therefore, if the temperature-sensitive oscillator 22 oscillates at IμA for tm _sec once, its average current consumption is It/128000 (μA).
becomes. In actual experimental circuits, this value is less than 10 μA.

The output signal of the gate 70 is the signal shown in FIG. The temperature-sensitive oscillator 22 starts oscillating in synchronization with the falling edge of the signal. On the other hand, since the driving timing of the motor is synchronized with the falling edge of the 1 Hz signal, the driving of the motor and the oscillation of the temperature-sensitive oscillator 22 do not occur at the same time. Therefore, there is no adverse effect caused by both occurring at the same time, such as an excessive drop in battery voltage or a drop in oscillation. Also, when the 1Hz signal is H, the selector 20, which will be described later,
The output of the LATCH 30 is selected, and when the signal is L, the signal of the decoder 36 is selected and output. The output of LATCH30 changes when the temperature-sensitive oscillator 22 oscillates and a change in temperature is detected, but since the temperature-sensitive oscillator oscillates when the 1Hz signal is L, the output of LATCH30 from the selector 20 changes. The output of LATCH30 does not change while it is being output. Therefore, no problem occurs in the operation of the coincidence detection circuit 16.

DFF78 and gate 80 are compensation limit detection circuit 3
This is a circuit that creates a signal to perform the initial reset in step 2.
When the output of DFF74 falls, a thin pulse is output in synchronization with this.

The variable frequency divider circuit 24 counts the output signal of the temperature-sensitive oscillator 22 with a counter 84 . When the final stage Q output of the counter 84 is H, if the contents set at the external terminals _S1 to _S8 match the contents of the counter 84, a coincidence detection circuit consisting of an exclusive OR circuit group 85 and a gate 86 detects a coincidence. Detected. When the DFF 88 reads the match signal, it resets the counter 84.
When the counter 84 is reset, the Q output of the final stage falls, so the DFF 90 is triggered and the Q output of the DFF 90 rises. DFF92, inverter 94,
The gate 82 is a circuit that creates a thin pulse signal periodically at the rising edge of the Q output of the DFF 90, and this signal is applied to the reset end of the DFF 74 via the OR gate 76. Therefore, the output of DFF74 is H
As a result, the temperature-sensitive oscillator 22 is stopped. gate 82
The pulse signal output from the ROM28 and
Applied to the clock terminal of LATCH30.
The signal activates the ROM28,
LATCH30 reads data from ROM28.

The terminals S ₁ to _{S 8} correspond to the division ratio setting means shown in FIG. ₁ , and the _{temperature -} sensitive oscillator 2 is
The time T from when the gate 82 starts oscillating until the signal is output from the gate 82 is adjusted. In this example circuit, the resistances R ₁ , R ₂ and capacitance of the temperature-sensitive oscillator 22
C ₁ and C ₂ are formed within the integrated circuit. This eliminates the problem of frequency shifts due to aging and humidity within the watch. However, since the resistance and capacitance values within the integrated circuit naturally vary, the oscillation frequency of the temperature-sensitive oscillator 22 will differ depending on the IC. The S ₁ to _{S 9} terminals are provided to absorb this variation, and the resistance value and frequency division ratio are set so that the time T becomes constant at a predetermined temperature. In the circuit of this embodiment, the frequency division ratio of the variable frequency divider circuit 24 can be set from 1/256 to 1/511.

The TE terminal is provided for testing purposes, and when the potential of this terminal is set to H, the output of the gate 66 becomes H, so that the temperature-sensitive oscillator 22 oscillates continuously. The S ₀ terminal is a terminal for checking the period of the temperature-sensitive oscillator 22 in this state. By setting the S ₁ to S ₉ terminals in a predetermined state and measuring the period of the signal appearing at the S ₀ terminal, For setting the time T to a predetermined value
Understand the conditions of S ₁ to S ₉ terminals. Of course, this measurement must be performed at a predetermined temperature.

96 is a battery insertion detection circuit which outputs a thin pulse signal in response to insertion of a battery.

The signal resets the first and second stage frequency dividers of the oscillation control circuit 72, sets the third and subsequent stage frequency dividers,
Reset DFF74 and set DFF88. The counter 84 is reset by setting the DFF 88. By setting in this way, the oscillation control circuit 20, the temperature-sensitive oscillator 22,
The variable frequency divider circuit 24 is in a steady state when the temperature-sensitive oscillator 22 stops oscillating. Since only the first and second stages of the frequency divider 72 are reset, and the third and subsequent stages are set, after the power-on detection pulse is generated, the gate 70 is reset.
When three pulse signals are output from
The output falls and the temperature sensitive oscillator 22 starts oscillating.
Therefore, temperature detection will be performed approximately 3 seconds after battery insertion, and temperature compensation will be performed.

The output of the frequency divider circuit 4 is always applied to the address input terminal of the ROM 28. The temperature-sensitive oscillator 22 starts oscillating in synchronization with the rising edge of the 2Hz signal.
2K applied to the address input terminal of ROM28
All divided outputs from Hz to 64Hz are low at the start of oscillation.
It is becoming. Therefore, the address specified after oscillation starts is determined by time. The time T from when the temperature-sensitive oscillator 22 starts oscillating until a signal is output from the variable frequency divider circuit 24 monotonically changes depending on the temperature. This is due to the temperature characteristics of the diffused resistor used in the temperature-sensitive oscillator 22, and therefore the designated address of the ROM 28 when a read signal is applied to the LATCH 30 is determined by the temperature.
Each address of the ROM 28 stores temperature compensation data required for the corresponding temperature. Therefore, as soon as the temperature-sensitive oscillator finishes oscillating, LATCH3
0 is loaded with temperature compensation data required at the temperature at that time.

FIGS. 7 and 8 show one embodiment of the circuit of the ROM 28. Since the ROM 28 has a 6-bit address structure, the temperature within the compensation limit is divided into 64 parts, and the optimum correction data for each temperature range is stored in each address.

FIG. 7 shows an address selection section which creates address signals A ₁ to A ₆₄ from signals IN ₁ to _{IN 6} sent from the frequency divider 4. One end of the 13 N-channel transistors connected in series is connected to the high potential side via a resistor, and the other end is connected to the low potential side. The IN ₁ to IN ₆ signals, their inverted signals, and the φ signal are applied to the gates of the 13 N-channel transistors connected in series. Series transistors having such a configuration are prepared for the number of address signals required (64 in this example). This transistor array has a ROM structure, and unnecessary transistors have their sources and drains shorted during the manufacturing process or are of a depletion type. That is, one of the transistors to which the IN _N signal is applied and the transistor to which the IN _N signal is applied is manufactured so as to act as a conductor.
In this way, seven transistors are actually connected in series. The φ signal is a signal that activates the ROM 28 and becomes H for a short time when data needs to be read. When the φ signal becomes H, all series transistors of only one set in the entire series transistor array are turned on, and the output signal A _N becomes L. Therefore, current flows through the series transistor and resistor only during the short period when the φ signal is at H level. Address signal A is sent to the circuit section of FIG.

In Figure 8, each output line OUT1 to OUT6
are connected to L through a resistor, and connected to H through transistors provided corresponding to each address signal _A1 to _A64 . The transistor becomes conductive when the corresponding address signal A _N becomes L, causing the output line to become H. Address signal is L
Since this occurs when the φ signal is at H, current flows through the resistor and transistor only during the short period when the φ signal is at H.

The transistor group is created during IC manufacturing so that the Vth of unnecessary transistors is higher than the power supply voltage. In other words, the Vth of the transistor whose output data should be set to L is set to a high value, and the Vth of the transistor whose output data is set to be set to H is set to the normal Vth. It is possible to set Vth high using ordinary techniques such as increasing the thickness of the gate oxide film of the MOS transistor.

The output of the LATCH 30 and the output of the decoder 36 are input to the selector 20, and when the 1Hz signal is H, the former is selectively outputted, and when the 1Hz signal is L, the latter is selectively outputted and sent to the coincidence detection circuit 4.

The match detection circuit 16 compares the data sent from the selector 20 and the contents of the frequency divider circuit 4 using an exclusive OR circuit group 98, and if all the signals match, the NAND
A match signal is output from the gate 102 in synchronization with the output of the gate 100.

In the normal state, the DFF 104 of the switch control circuit 14 is triggered by a 2 Hz signal applied through the select gate 106 and reset by the coincidence detection signal. The output of the DFF is applied to the control terminal of the switch 12 of the crystal oscillation circuit 2 via the NAND gate 108 and the inverter group 110. Therefore, when the DFF 104 is triggered and the output becomes L, the switch 12 is turned OFF, and when it is reset and the output becomes H, the switch 12 is turned ON. The switch is OFF from the time the 2Hz signal falls until the coincidence detection signal is output, and the switch is ON from the time the coincidence detection signal is output until the 2Hz signal falls, so the switch ON time and switch OFF time are The ratio, that is, the ratio of the oscillation time at ₁ and the oscillation time at ₂ in FIG. 2 is determined by the data output from the selector 20. If a large code is output from the selector 20, it will take time for the coincidence detection signal to be output, so the average frequency of the reference signal output from the crystal oscillator 2 will be close to ₂ , and conversely, a small code will be output. In this case, the frequency will be close to ₁ . Therefore, a relatively small code is written in the address of the ROM 28 corresponding to the temperature around t ₀ in FIG. 2, and a relatively large code is written in the address of the ROM 28 corresponding to the temperature around t ₁ and t ₂ . It is written.

Oscillation is more stable if the input side capacitance of the crystal oscillation circuit 2 is kept small while the battery voltage is fluctuating due to motor drive. Furthermore, if the change in battery voltage and the switching timing of the switch 12 coincide, there is a risk of miscounting due to bias change. The switch control circuit 14 is provided for this purpose.
Protection circuit means 113 consisting of DFF 116, NAND gate 118, inverters 112, 114, NAND gate 108 and DFF 50 in frequency divider circuit 4
It is. The output waveform diagram of NAND gate 118 is shown in Figure 9.
As shown in the figure. As is clear from FIG. 9, the output of the NAND gate 18 is L while the motor is being driven. Since this output is applied to the NAND gate 108, the switch 12 is fixed to OFF while it is at L.

32 is a compensation limit detection circuit.

If the difference between the reference signals when the switch 12 is ON and OFF is set to 50 ppm, the time for controlling the switch 12 for temperature compensation is half of the total, so the maximum temperature compensation amount is 25 ppm. 32K
When using a standard crystal oscillator that oscillates at about Hz, the temperature from the temperature at which the temperature coefficient becomes 0 to the temperature at which the frequency becomes 25 ppm lower than the frequency at that temperature is approximately 27.2°C. The temperature at which the temperature coefficient becomes 0 is 24℃
Then, the compensation limit temperature will be -3.2℃ and +51.2℃. If the time T from when the temperature-sensitive oscillator 22 starts oscillating to when the output is output from the variable frequency divider circuit 24 is adjusted to 36 m _sec at 24°C, from the actual measurement data, -
At 3.2°C, the time T is 28.440 m _sec , +51.2°C
It is 44.064 m _sec . The first diagram shows the state of the output of the frequency divider circuit 4 in this state.
This is figure 0. Returning to circuit block 32,
The DFFs 124 and 128 are reset by the output of the gate 80 at the same time as the temperature-sensitive oscillator 32 starts oscillating.
The DFF 124 is for determining whether the current temperature is above or below -3.2°C. When the time T when the temperature is -3.2°C has elapsed, it is triggered by the clock signal created by the gates 120 and 122, and the Q output becomes H. .
The DFF 128 is for determining whether the current temperature is above or below +51.2°C. When the time T when the temperature is +51.2°C has elapsed, it is triggered by the clock signal created by the gates 120 and 126, and the output becomes L. Become.
The NAND gate 130 is a gate that determines whether the current temperature is within the compensation limit, and the output of this gate is L when the time T is a value corresponding to a temperature between -3.2°C and +51.2°C. It becomes H when . FIG. 11 shows this relationship.

The DFF 132 is activated by the output of the variable frequency divider circuit 24 after a time T from the start of oscillation of the temperature-sensitive oscillator 22.
Read the output of NAND gate 130. Therefore, applicable
The Q output of the FF132 is L when the temperature is between -3.2°C and +51.2°C, and H otherwise.
The Q output of the DFF 132 and a 1Hz signal are applied to the NAND gate 134. This is because the timing for controlling the switch 12 for temperature compensation is only when 1 Hz is H. (When the 1Hz signal is H, the LATCH30 signal is output from the selector 20) The output of the NAND gate 134 is NAND
applied to gate 108. Therefore, when the temperature exceeds the compensation limit, the switch 12 is fixed to OFF during the temperature compensation timing (while the 1 Hz signal is H).

₁ to ₇ are terminals for adjusting the initial value of the frequency of the crystal oscillator 2. Terminals ₁ to ₅ are connected to readjustable mechanical switch means (hereinafter referred to as a cord trimmer), and terminals ₆ and ₇ are fixed in state. ₁ to ₅ are in charge of the lower 5 bits of the signal sent to the coincidence detection circuit 16, and ₆ and ₆ are in charge of the upper 1 bit. The codes shown in FIG. 12 are input from ₁ to ₅ , and the codes are sent to the decoder 3.
6, it is converted into binary codes O ₁ to O ₅ shown in FIG.

FIG. 13 is a circuit diagram of an embodiment of the decoder 36.

In FIG. 12, if the code of the O ₁ to O ₅ signals is small, the match detection circuit 16 outputs the match detection signal in a short time, and if the code is large, the match detection signal is output in a relatively long time. Therefore, if you increase the code, the clock will move forward, and if you decrease the code, the clock will move backward.

The circuit block 138 is a circuit for creating a signal of the most significant bit selected by the _6th and _7th terminals, and the 14th bit is output from the gates 140 and 142, respectively.
The signal shown in the figure is output and input to the selector I144. The selector I144 also receives L and H potentials as inputs. Terminal ₆ ,
₇ , one of the four inputs is selected and output. The signal output from the selector I 144 is sent to the coincidence detection circuit 16 via the selector 20.
and is compared with the 2Hz signal output from the frequency divider circuit 4. The timing at which each input of the selector I 144 and the 2Hz signal coincide is shown in FIG. In other words, the L signal coincides with the 2Hz signal at the timing between the arrows shown in
The output of gate 1 is at the timing shown in
The output signal 42 and the H signal have the timings shown in FIG. Therefore, when one input is selected in steps ₆ and ₇ and the code is changed using the code trimmer, the timing at which the coincidence detection signal is output will be the arrow of the selected timing among the timings shown in Fig. 14. You will be moving within the range. Since the timings shown in . . . , respectively, have overlapping portions, even if the most significant bit is fixed, there is no possibility that an unadjustable region will be created.

When the TE terminal is set to H, it enters test mode, but
At this time, the DFF 32 in the compensation limit detection circuit 32 is reset. This changes the control state of switch 12.
This is to eliminate the influence of the compensation limit detection circuit 32 when observing at the SW terminal. Also, when the test mode is set, the select gate 10 of the switch control circuit 14
6 outputs a 1 Hz signal as a clock signal for the DFF 104. This was done to remove the influence of temperature compensation from the control signal of switch 12. Since the clock signal is a 1Hz signal, when the temperature compensation timing comes, that is, 1Hz.
DFF 104 is not triggered when the Hz signal goes high. Therefore, the switch 12 remains in the ON state throughout the temperature compensation timing.

To check the contents of ROM28, use LATCH
φ terminal, SW terminal where 30 read signals appear,
Use FC terminal and X _IN terminal. By applying a desired number of pulse signals to the X _IN terminal, a desired address of the ROM can be selected. Therefore, force the φ terminal to H.
By doing so, data at the address can be read into LATCH30. Therefore, by applying a fast forward signal to the FC terminal and observing the state of the SW terminal, ROM2
You can know the data stored in 8.

As is clear from the above description, according to the present invention, the oscillator can be kept in a stable state when driving the motor, which is highly effective.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of an electronic timepiece according to the present invention, Fig. 2 is a temperature characteristic diagram of the crystal oscillator used in this embodiment, Fig. 3 is a temperature characteristic diagram compensated by the present invention, and Fig. 4 A and B are circuit diagrams of an embodiment of an electronic timepiece according to the present invention, FIG. 5 is a circuit diagram of an embodiment of an input circuit, FIG. 6 is a timing chart, and FIGS.
An embodiment circuit diagram of the ROM, FIGS. 9 to 12 and 14 are timing charts and explanatory diagrams for explaining the operation, and FIG. 13 is an embodiment circuit diagram of the decoder. 34, 36... Code output means, 16... Coincidence detection circuit, 12... Switch, 14... Switch control circuit, 112, 114, 116, 118, 1
08...Circuit means, 13...Protection circuit means.

Claims (1)

[Claims] 1. An oscillator that generates a time reference signal, a frequency divider circuit that divides the frequency of the reference signal, and a motor drive circuit that drives a motor in response to the output of the frequency divider circuit.
An electronic timepiece equipped with a motor and a pointer-type display device driven by the motor, a code output means whose code can be changed manually, and a code output of the code output means and an output of the frequency dividing circuit. a coincidence detection circuit that detects coincidence; a switch that switches a capacitance value that determines the oscillation frequency of the oscillator; and a switch control circuit that controls the switch in response to the output of the frequency divider circuit and the output of the coincidence detection circuit; An electronic timepiece characterized by comprising: protection circuit means that responds to the output of the frequency dividing circuit and maintains the switch in a constant state during the drive timing of the motor.