JPS6226433B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece with a temperature compensation function.

BACKGROUND ART In recent years, as crystal oscillation circuits have been used as time standards for electronic watches, and the timekeeping accuracy of watches has improved, temperature compensation of the crystal oscillation circuits has become an essential issue in further improving timekeeping accuracy.

An object of the present invention is to provide an electronic timepiece equipped with a novel temperature compensation method suitable for electronic timepieces.

A detailed explanation will be given below based on the drawings.

FIG. 1 is a block diagram of an embodiment of an electronic timepiece according to the present invention.

In FIG. 1, 2 is a crystal oscillation circuit, and the reference signal output from this circuit is divided by a frequency dividing circuit 4 to 1
The Hz signal is sent to the motor drive circuit 6. The drive circuit 6 drives a motor 8, and the motor 8 operates the pointer type display device 10.

The oscillation circuit 2 has an electronic switch 12, by which the input capacitance can be changed. Figure 2 shows the frequency of crystal oscillation circuit 2.
This is a diagram showing temperature characteristics, but when switch 12 is
When turned ON, the input capacitance increases, so see Figure 2.
It oscillates at a relatively low frequency shown in ₁ , and the switch 1
When 2 is turned OFF, the input capacitance becomes smaller, so oscillation occurs at a relatively high frequency as shown in _FIG . Therefore, by changing the ratio of the time when the switch 12 is turned on and the time when it is turned off, a frequency between ₁ and ₂ can be obtained. In this embodiment, initial frequency adjustment and temperature compensation of the crystal oscillation circuit 2 are performed by controlling the switch 12.

The switch 12 is controlled by a switch control circuit 14.
Controlled ON and OFF. Switch control circuit 14
Turn on switch 12 at the beginning of each unit time or
OFF, and this state is canceled by the coincidence signal from the coincidence detection circuit 16. Coincidence detection circuit 16 is connected to line 18
It compares the output group of the selector 21 and the output of the frequency dividing circuit 4 sent to it, and if they match, outputs a match signal. Therefore, the signal on line 18 causes switch 12 to
The ON/OFF time ratio changes, and as a result, the average frequency of the reference signal output from the crystal oscillation circuit 2 changes. In this way, the frequency adjustment means 1 is composed of the electronic switch 12, the switch control circuit 14, and the coincidence detection circuit 16.

A temperature-sensitive oscillator 22 has a ring oscillator configuration whose cycle is determined by a temperature-sensitive resistor and a capacitance. The oscillation control circuit 20 controls the oscillation of the temperature-sensitive oscillator 22,
This is a circuit that controls stopping, and the temperature-sensitive oscillator 22 is activated intermittently.
Outputs the oscillation start command. The reason for intermittent oscillation is mainly to reduce the average power consumption of the temperature-sensitive oscillator 22. In FIG. 1, the temperature-sensitive oscillator 22
The variable frequency divider circuit 24 plays the role of a counter that counts the outputs of , and outputs a signal when a predetermined number is reached. The variable frequency divider circuit 24 is the frequency division ratio setting means 2
When the number of pulse signals set in 6 is sent from the temperature-sensitive oscillator, an output signal is output, and in response to the signal, the oscillation control circuit 20 stops the temperature-sensitive oscillator 22. The frequency division ratio setting means 26 is provided to absorb variations in the oscillation frequency of the temperature-sensitive oscillator 22, and the frequency division ratio setting means 26 changes the frequency division ratio of the variable frequency division circuit 24 to make the frequency division ratio variable. The period-temperature characteristics of the output signal of the frequency dividing circuit 24 are adjusted to a constant value. Since 22 is a temperature-sensitive oscillator, variable frequency dividing circuit 2
The period of the output signal No. 4, that is, the time from when the temperature-sensitive oscillator 22 starts oscillating until it outputs a desired number of pulse signals, changes depending on the temperature. Therefore, the temperature can be determined from the time.

The ROM 28 stores data for temperature compensation. This data is used to change the ratio between the ON time and OFF time of the switch 12 in response to temperature changes, and is required by the coincidence detection circuit in order to obtain the desired ratio.
The output data of ROM 28 is read into latch 30, which is a volatile memory. The output of the frequency dividing circuit 4 is connected to the address signal end of the ROM 28.
Since the temperature-sensitive oscillator 22 starts oscillating in response to the output of the frequency dividing circuit 4, the internal state of the frequency dividing circuit 4 is constant when oscillation starts. Therefore, after a certain period of time after the temperature-sensitive oscillator 22 starts oscillating,
This means that the ROM 28 is designated with a fixed address. Latch 30 reads the output data of ROM 28 in response to the output signal of variable frequency divider circuit 24. As mentioned above, the time from the start of oscillation of the temperature-sensitive oscillator 22 until the output of the variable frequency divider circuit 24 changes depending on the temperature. will be loaded. Therefore, if temperature compensation data necessary for each temperature is written in each address of the ROM, the temperature compensation data will be read into the latch 30 each time the temperature-sensitive oscillator 22 oscillates. In addition
The φ signal sent to the ROM 28 is for reducing the power consumption of the ROM, and the ROM 28 is activated only while the φ signal is present, that is, only when ROM data is read into the latch 30.
The temperature compensation data read into the latch 30 is sent to the coincidence detection circuit 16 via the selector 21.

FIG. 3 shows the frequency-temperature characteristics when temperature compensation is performed in this manner. In the characteristics shown in FIG. 3, the amplitude of the vertical axis can be made smaller as the resolution of the temperature to be detected is increased and the resolution of the temperature compensation data sent to the coincidence detection circuit 16 is increased. In order to increase the resolution of the detected temperature, it is necessary to increase the number of words in the ROM 28, and in order to increase the resolution of temperature compensation data, it is necessary to increase the number of bits constituting a word.

Compensation reaches its limit beyond the temperature at which curve ₂ in FIG. 3 coincides with the desired frequency. In other words, when t is less than ₁ and more than t ₂ in Figure 3, it becomes _1.
With the combination of (2) and ₍₂₎ , it becomes impossible to create the desired frequency. In such a case, switch 12 should be turned on to reduce the error from the desired frequency.
Fix it to OFF and set the output frequency of crystal oscillator circuit 2.
It is desirable to fix the characteristics to ₂ . A compensation limit detection circuit 32 is provided for this purpose. The compensation limit detection circuit 32 detects, based on the signal from the frequency dividing circuit 4, that the time from when the temperature-sensitive oscillator 22 starts oscillating to when the variable frequency dividing circuit 24 outputs an output signal exceeds a certain range. . The detection signal is sent to the switch control circuit 14, and the switch 12 is turned off in response to the detection signal.

The code output means 34 is provided to adjust the initial value of the oscillation frequency of the crystal oscillation circuit 2. The signal of the code output means 34 is converted into a desired signal by the decoder 36, and the match is detected via the selector 20. The signal is sent to circuit 16. Therefore, the average oscillation frequency of the crystal oscillation circuit 2 can be controlled by the signal from the code output means 34.

The selector 21 selectively sends the temperature compensation data and initial value adjustment data to the coincidence detection circuit 16 in response to the periodic signal from the frequency dividing circuit 4. Shown in Figures 2 and 3
The frequency difference between ₁ and ₂ is 2Δ, and the duty cycle of the periodic signal applied to the selector 21 is 50%.
If so, it becomes possible to adjust Δ in both temperature compensation and initial value frequency adjustment.

4A and 4B are circuit diagrams of an embodiment of an electronic timepiece according to the present invention, showing circuit parts that can be integrated within the block 3. FIG. Note that blocks corresponding to those in FIG. 1 are given the same numbers.

The reference signal output from the crystal oscillation circuit 2 is input to a 15-stage frequency divider via an inverter 40 for waveform shaping, and a 1 Hz signal is obtained from the final stage frequency divider 42. The output of the fifth-stage frequency divider 44 is taken out from the integrated circuit as an FC terminal, and is connected to a data type flip-flop (hereinafter referred to as DFF), which is used as a fast-forward signal input terminal for checking the oscillation frequency and circuit function check. (abbreviated) 46 is provided to create the time width of the signal that drives the motor, and the output of the DFF 46 rises at the same time as the output of the frequency divider 42 falls, and is reset in response to the output of the gate 48. Therefore, the period is 1 second and the pulse width is approximately 5.9 msec. The DFF 50 is provided to ensure that the motor drive timing and the switching timing of the oscillation circuit switch 12 do not match, and the phase is delayed by rereading the output of the DFF 46 using a 512Hz signal.
The output of DFF50 is the motor drive circuit block 6.
As a result, drive pulses are output alternately from the OUT1 and OUT2 terminals.

22 is a temperature-sensitive oscillator and inverters 52, 54, 5
6, 58, 60) NAD gate 62 resistors R ₁ , R ₂ ,
It includes a multivibrator consisting of capacitors C ₁ and C ₂ and a gate 66 switch 64. The oscillation frequency of the multivibrator is determined by the time constants of R ₁ , R ₂ .C ₁ and C ₂ . R ₁ and R ₂ use diffused resistance
Both C ₁ and C ₂ can be integrated by using gate capacitance. The temperature characteristic of diffused resistance is approximately per 1°C.
Since the temperature coefficient is 0.7%, which is sufficiently large compared to the gate capacitance, the temperature characteristics of the period of the multivibrator are almost equal to the temperature characteristics of the diffused resistor. NAMD
Gate 62 is a gate for controlling oscillation and stopping of the multivibrator. When the output of gate 66 inputted to NAND gate 62 becomes H, the multivibrator starts oscillating, and when it becomes L, it stops oscillating.
The switch 64 is provided for adjusting the oscillation frequency of the multivibrator.
When turned ON, resistor _R2 is shorted. If R ₁ and R ₂ are set to approximately equal values, the oscillation frequency can be approximately doubled by shorting the switch 64. Switch 64 is controlled by a signal applied to terminal _S9 . Note that the input circuit 68 is composed of a circuit shown in FIG. Terminal C is an input/output terminal for checking the frequency of the multivibrator and checking the operation of the variable frequency divider circuit 24.

The oscillation control circuit 20 is a circuit for causing the temperature-sensitive oscillator 22 to oscillate intermittently.The signal from the frequency dividing circuit 4 is synthesized by a gate 70, and the synthesized signal is frequency-divided by a seven-stage frequency divider 72. Create a signal with a period of seconds.
The DFF 74 is triggered by the rising edge of the composite signal and outputs an oscillation start command for the temperature-sensitive oscillator. The composite signal is applied to one input of the gate 66, and since the output of the barrier gate 66 becomes H, the temperature-sensitive oscillator 22
starts oscillating. When the temperature-sensitive oscillator 22 outputs a predetermined number of pulse signals, the variable frequency divider circuit block 2
A signal is output from the gate 82 of No. 4, and the signal is
Applied to the reset end of DFF 74 via OR gate 76. As a result, the output of DFF becomes H and the output of gate 66 becomes L, so temperature-sensitive oscillator 22
stops oscillation. In this way, the temperature-sensitive oscillator 2
2 oscillates every 128 seconds and automatically stops after outputting a predetermined number of pulse signals. Therefore, if the temperature-sensitive oscillator 22 oscillates once at IμA for tm sec, its average current consumption is It/128000 (μA).
becomes. In actual experimental circuits, this value is less than 10 μA.

The output signal of the gate 70 is the signal shown in FIG. The temperature-sensitive oscillator 22 starts oscillating in synchronization with the falling edge of the output signal. On the other hand, since the driving timing of the motor is synchronized with the falling edge of the 1 Hz signal, the driving of the motor and the oscillation of the temperature-sensitive oscillator 22 do not occur at the same time. Therefore, there is no adverse effect caused by both occurring at the same time, such as an excessive drop in battery voltage or a drop in oscillation. Also, when the 1Hz signal is H, the selector 23, which will be described later,
The output of the LATCH 30 is selected, and when the signal is L, the signal of the demarder 36 is selected and output. The output of LATCH30 changes when the temperature-sensitive oscillator 22 oscillates and a change in temperature is detected, but since the temperature-sensitive oscillator oscillates only when the 1Hz signal is L, the output of LATCH30 is output from the selector 23. The output of LATCH30 does not change when the Therefore, no problem occurs in the operation of the coincidence detection circuit 16.

DFF78 and gate 80 are compensation limit detection circuit 3
This is a circuit that creates a signal to perform the initial reset in step 2.
When the output of DFF74 falls, a thin pulse is output in synchronization with this.

The variable frequency divider circuit 24 counts the output signal of the temperature-sensitive oscillator 22 with a counter 84 . When the final stage Q output of the counter 84 is H, if the contents set at the external terminals _S1 to _S8 match the contents of the counter 84, a coincidence detection circuit consisting of an exclusive OR circuit group 85 and a gate 86 detects a coincidence. Detected. When the DFF88 reads the signal created by the coincidence detection circuit, the counter 8
Reset 4. When the counter 84 is reset, the Q output of the final stage falls, so the DFF 90 is triggered and the Q output of the DFF 90 rises. DFF9
2. The inverter 94 and gate 82 are circuits that create a thin pulse signal synchronized with the rise of the Q output of the DFF 90, and this pulse signal is applied to the reset end of the DFF 74 via the OR gate 76. Therefore, the output of DFF74 becomes H and temperature-sensitive oscillator 2
Stop 2. The pulse signal output from gate 82 is also applied to the clock terminals of ROM 28 and LATCH 30. RCM by pulse signal
28 becomes active, LATCH30 becomes ROM2
Read the data of 8.

The terminals S ₁ to _{S 8} correspond to the division ratio setting means shown in FIG. ₁ , and the _{temperature -} sensitive oscillator 2 is
The time T from when the gate 82 starts oscillating until the signal is output from the gate 82 is adjusted. In this example circuit, the resistances R ₁ , R ₂ and capacitance of the temperature-sensitive oscillator 22
C ₁ and C ₂ are formed within the integrated circuit. This eliminates the problem of frequency shifts due to aging and humidity within the watch. However, since the values of resistance and capacitance within the integrated circuit naturally vary, the oscillation frequency of the temperature-sensitive oscillator 22 will differ depending on the IC. The S ₁ to _{S 9} terminals are provided to absorb this variation, and the resistance value and frequency division ratio are set so that the time T becomes constant at a predetermined temperature. In this embodiment circuit, the frequency division ratio of the variable frequency divider circuit 24 is from 1/256 to 1/256.
It is possible to set up to 511.

The TF terminal is provided for testing purposes, and when its potential is set to H, the output of the gate 66 becomes H, so the temperature-sensitive oscillator 22 oscillates continuously. The S ₀ terminal is a terminal for checking the period of the temperature-sensitive oscillator 22 in this state. By setting the S ₁ to S ₉ terminals in a predetermined state and measuring the period of the signal appearing at the S ₀ terminal, , S ₁ for setting the time T to a predetermined value
~ Understand the conditions of the _S9 terminal. Of course, this measurement must be performed at a predetermined temperature.

96 is a battery insertion detection circuit which outputs a thin pulse signal in response to insertion of a battery.

The pulse signal is transmitted to the first stage of the oscillation control circuit 72,
The frequency divider of the stage is reset, the frequency dividers of the third and subsequent stages are set, the DFF 74 is reset, and the DFF 88 is set. The counter 84 is reset by setting the DFF 88. With this setting, the oscillation control circuit 20, temperature-sensitive oscillator 22, and variable frequency dividing circuit 24 are in a steady state when the temperature-sensitive oscillator 22 stops oscillating. The frequency divider 72 is the first stage, 2
Since only the stage is reset and the third and subsequent stages are set, when three pulse signals are output from the gate 70 after the power-on detection pulse is generated, the Q output of the final stage falls and the temperature-sensitive oscillator 22 starts oscillating. Therefore, temperature detection is performed approximately 3 seconds after the battery is turned on, and temperature compensation is performed.

The output of the frequency divider circuit 4 is always applied to the address input terminal of the ROM 28. The temperature-sensitive oscillator 22 starts oscillating in synchronization with the rising edge of the 2Hz signal.
2K applied to the address input terminal of ROM28
All divided outputs from Hz to 64Hz are low at the start of oscillation.
It is becoming. Therefore, the address specified after oscillation starts is determined by time. The time T from when the temperature-sensitive oscillator 22 starts oscillating until a signal is output from the variable frequency divider circuit 24 monotonically changes depending on the temperature. This is due to the temperature characteristics of the diffused resistor used in the temperature-sensitive oscillator 22, and therefore the designated address of the ROM 28 when a read signal is applied to the LATCH 30 is determined by the temperature.
Each address of the ROM 28 stores temperature compensation data required at the corresponding temperature. Therefore, as soon as the temperature-sensitive oscillator finishes oscillating, LATCH3
0 is loaded with temperature compensation data required at the temperature at that time.

FIGS. 7 and 8 show one embodiment of the circuit of the ROM 28. Since the ROM 28 has a 6-beat address structure, the temperature within the temperature limit is divided into 64 parts, and the optimum correction data for each temperature range is stored in each address.

FIG. 7 shows an address selection section which creates address signals A ₁ to A ₆₄ from signals IN ₁ to _{IN 6} sent from the frequency divider 4. One end of the 13 N-channel transistors connected in series is connected to the high potential side via a resistor, and the other end is connected to the low potential side. The IN ₁ to IN ₆ signals, their inverted signals, and the φ signal are applied to the gates of the 13 N-channel transistors connected in series. Series transistors having such a configuration are prepared for the number of address signals required (64 in this example). This transistor array has a ROM structure, and unnecessary transistors are shorted between the lease and drain during the manufacturing process, or are of a depletion type. That is, one of the transistors to which the IN _N signal is applied and the transistor to which _{the N} signal is applied is manufactured so as to act as a conductor. In this way, seven transistors are actually connected in series. The φ signal is a signal that activates the ROM 28 and becomes H for a short time when data needs to be read. φ signal is H
Out of all the series transistor arrays, all the series transistors in one set are ON and the output signal A _N
becomes L.

Therefore, current flows through the series transistor and resistor only during the short period when the φ signal is at H level. Address signal A is sent to the circuit section of FIG.

In FIG. 8, each of the output lines OUT1 to OUT6 is connected to L through a resistor, and to H through transistors provided corresponding to each address signal _A1 to _A64 .

This transistor has a corresponding address signal A _N
When becomes L, it becomes conductive and the output line becomes H. Since the address signal becomes L when the φ signal is H, current flows through the resistor and transistor only during the short period when the φ signal is H.

The transistor group is created during IC manufacturing so that the Vth of unnecessary transistors is higher than the power supply voltage. In other words, the Vth of the transistor whose output data should be set to L is set to a high value, and the Vth of the transistor whose output data is set to be set to H is set to the normal Vth. It is possible to set Vth high using ordinary techniques such as increasing the thickness of the gate oxide film of the MOS transistor.

The output of the LATCH 30 and the output of the decoder 36 are input to the selector 23, and when the 1 Hz signal is H, the former is selectively outputted, and when the 1 Hz signal is L, the latter is selectively outputted and sent to the coincidence detection circuit 4.

The match detection circuit 16 compares the data sent from the selector 23 with the contents of the frequency divider circuit 4 using an exclusive OR circuit group 98, and if all the signals match, the NAND
A match signal is output from the gate 102 in synchronization with the output of the gate 100.

In the normal state, the DFF 104 of the switch control circuit 14 is triggered by a 2 Hz signal applied through the select gate 106 and reset by the coincidence detection signal. Moreover, the output of DFF is NAND gate 108, inverter group 110
The voltage is applied to the control terminal of the switch 12 of the crystal oscillation circuit 2 via the oscillator circuit 2. Therefore, when the DFF 104 is triggered and the output becomes L, the switch 12 is turned OFF.
When it is reset and the output becomes H, the switch 12 is turned on. The switch is OFF from the time the 2Hz signal falls until the coincidence detection signal is output, and the switch is ON from the time the coincidence detection signal is output until the 2Hz signal falls, so the ratio of the switch ON time to the switch OFF time is That is, the ratio of the oscillation time at ₁ and the oscillation time at ₂ in FIG. 2 is determined by the data output from the selector 23. When a large code is output from the selector 23, it takes time to output the coincidence detection signal.The average frequency of the reference signal output from the crystal oscillator 2 becomes a frequency close to ₂ , and conversely, a small code is output. If it is, the frequency will be close to ₁ . Therefore, it corresponds to the temperature near t ₀ in Figure 2.
Relatively small codes are written in the addresses of the ROM 28, and relatively large codes are written in the addresses of the ROM 28 corresponding to temperatures around ₁ and ₂ .

Oscillation is more stable if the input side capacitance of the crystal oscillation circuit 2 is kept small while the battery voltage is fluctuating due to motor drive. Furthermore, if the change in battery voltage and the switching timing of the switch 12 coincide, there is a risk of miscounting due to bias change. The switch control circuit 14 is provided for this purpose.
A circuit consisting of a DFF 116, a NAND gate 118, and inverters 112 and 114, which is the output
An output waveform diagram of the NAND gate 118 is shown in FIG. As is clear from Figure 9, the motor is running
The output of the NAND gate 118 is at L level. Since this output is applied to the NAND gate 108, the switch 12 is fixed to OFF while it is at L.

32 is a compensation limit detection circuit.

If the difference between the reference signals when the switch 12 is ON and OFF is set to 50 ppm, the time for controlling the switch 12 for temperature compensation is half of the total, so the maximum temperature compensation amount is 25 ppm. 32KHz
Using a standard crystal oscillator that oscillates at about
The temperature from the temperature where the temperature coefficient becomes 0 to the temperature where the frequency becomes 25ppm lower than the frequency at that temperature is approximately 27.2
It is ℃. If the temperature at which the temperature coefficient becomes 0 is 24°C, the compensation limit temperatures will be -3.2°C and +51.2°C. After the temperature-sensitive oscillator 22 starts oscillating, the variable frequency divider circuit 2
The time T from 4 to the output is set at 24℃.
When adjusted to 36m sec., from the actual measurement data, -3.2℃
The time T is 28.440 m sec., and 44.064 m sec. at +51.2°C. The first diagram shows the state of the output of the frequency divider circuit 4 in this state.
This is figure 0. Returning to circuit block 32,
The DFFs 124 and 128 are reset by the output of the gate 80 at the same time as the temperature-sensitive oscillator 22 starts oscillating.
The DFF 124 is for determining whether the current temperature is above or below -3.2°C. When the time T when the temperature is -3.2°C has elapsed, it is triggered by the clock signal created by the gates 120 and 122, and the Q output becomes H. .
The DFF 128 is for determining whether the current temperature is above or below +51.2°C. When the time T when the temperature is +51.2°C has elapsed, it is triggered by the clock signal created by the gates 120 and 126, and the output becomes L. Become.
The NAND gate 130 is a gate that determines whether the current temperature is within the compensation limit, and the output of this gate is L when the time T is a value corresponding to a temperature between -3.2°C and +51.2°C. It becomes H when . FIG. 11 shows this relationship.

The DFF 132 is activated by the output of the variable frequency divider circuit 24 after a time T after the temperature-sensitive oscillator 22 starts resonating.
Read the output of NAND gate 130. Therefore, applicable
The Q output of the FF132 is L when the temperature is between -3.2°C and +51.2°C, and H otherwise.
The Q output of the DFF 132 and a 1Hz signal are applied to the NAND gate 134. This is because the timing for controlling the switch 12 for temperature compensation is only when 1 Hz is H. (When the 1Hz signal is H, the LATCH30 signal is output from the selector 20) The output of the NAND gate 134 is the NAND gate 10
8. Therefore, when the temperature exceeds the compensation limit, the switch 12 is fixed to OFF during the temperature compensation timing (while the 1 Hz signal is H).

₁ to ₇ are terminals for adjusting the initial value of the frequency of the crystal oscillator 2. Terminals ₁ to ₅ are connected to readjustable mechanical switch means (hereinafter referred to as a cord trimmer), and terminals ₆ and ₇ are fixed in state. ₁ to ₅ are in charge of the lower 5 bits of the signal sent to the coincidence detection circuit 16, and ₆ and ₇ are in charge of the higher 1 bit. The codes shown in FIG. 12 are input from ₁ to ₅ , and the code shown in FIG.
It is converted into the binary code O ₁ to _{O 5} shown in the figure.

FIG. 13 is a circuit diagram of an embodiment of the decoder 36.

In FIG. 12, if the code of the O ₁ to O ₅ signals is small, the match detection circuit 16 outputs the match detection signal in a short time, and if the code is large, the match detection signal is output in a relatively long time. Therefore, if you make the code larger, the clock will move forward, and if you make the code smaller, the clock will move backward.

Circuit block 138 is a circuit for creating a signal of the most significant bit selected by terminals ₆ and _7. Signals shown in FIG. 14 are output from gates 140 and 12, respectively, and input to selector 144. The selector 144 also receives L and H potentials as inputs. terminals ₆ , ₇
Depending on the state, one of the four inputs is selected and output. The signal output from the selector 144 is sent to the coincidence detection circuit 16 via the selector 20 and compared with the 2Hz signal output from the frequency dividing circuit 4. The timing at which each input of the selector 144 and the 2Hz signal coincide is shown in FIG.
That is, the L signal coincides with the 2Hz signal at the timing between the arrows shown in , the output of the gate 140 is at the timing shown in
The output signal and the H signal have the timings shown in respectively. Therefore, when one input is selected in ₆ and ₇ and the code is changed by the code trimmer, the timing at which the coincidence detection signal is output will be the arrow of the selected timing among the timings shown in Fig. 14. You will be moving within the range. Since the timings shown in . . . , respectively, have overlapping portions, even if the most significant bit is fixed, there is no possibility that an unadjustable region will be created.

When the TE terminal is set to H, it enters test mode, but
At this time, the DFF 132 in the compensation limit detection circuit 32 is reset. This is done by the compensation limit detection circuit 32 when observing the control state of the switch 12 at the SW terminal.
This is to eliminate the influence of Also, when the test mode is set, the select gate 1 of the switch control circuit 14
06 outputs a 1Hz signal as the clock signal for the DFF104. This was done to remove the influence of temperature compensation from the control signal of switch 12. Since the clock signal is a 1Hz signal, when the temperature compensation timing comes, that is, when the 1Hz signal becomes H, the DFF 104 is triggered. Not done. Therefore, the switch 12 remains in the ON state throughout the temperature compensation timing.

To check the contents of ROM28, use LATCH
φ terminal, SW terminal FC where 30 read signals appear
terminal, use the X _IN terminal. By applying a desired number of pulse signals to the X _IN terminal, a desired address of the ROM can be selected. Therefore, by forcibly setting the φ terminal to H, data at the address can be read into the LATCH 30. Therefore, by applying a fast forward signal to the FC terminal and observing the state of the SW terminal, the data stored in the ROM 28 can be known.

As is clear from the above description, according to the present invention, temperature compensation of a quartz watch can be achieved without any external parts, and is highly effective. Furthermore, since a method is adopted in which current is passed through the read-only memory only for a short period of time, power consumption can be reduced, making it particularly suitable for electronic watches powered by small and low-capacity batteries.

Note that the temperature compensation method of the present invention uses temperature compensation data.
Since it is written in ROM, it is possible to compensate for any temperature characteristics of the crystal oscillator as long as it is reproducible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of an electronic timepiece according to the present invention, Fig. 2 is a temperature characteristic diagram of the crystal oscillator used in this embodiment, Fig. 3 is a temperature characteristic diagram compensated by the present invention, and Fig. 4 A and B are circuit diagrams of an embodiment of an electronic timepiece according to the present invention, FIG. 5 is a circuit diagram of an embodiment of an input circuit, FIG. 6 is a timing chart, and FIGS.
ROM embodiment circuit diagrams, Figures 9 to 12 and 14
The figures are a timing chart and an explanatory diagram for explaining the operation, and FIG. 13 is a circuit diagram of an embodiment of the decoder. 1... Frequency adjustment means, 22... Temperature-sensitive oscillator, 20
...Oscillation control circuit, 24...Counter, 28...Read-only memory, 30...Volatile memory.

Claims (1)

[Scope of Claims] 1. An electronic watch that includes a time reference signal generation circuit that generates a time reference signal, a frequency division circuit that divides the frequency of the reference signal, a drive circuit that drives a time display device, and a time display device. a temperature-sensitive oscillator; an oscillation control circuit that intermittently oscillates the temperature-sensitive oscillator in response to the output of the frequency dividing circuit; and a temperature-sensitive oscillator that counts the output of the temperature-sensitive oscillator and outputs a signal when a predetermined number is reached. a read-only memory to which the output of the frequency divider circuit is applied to an address input terminal; a volatile memory that stores the output of the read-only memory in response to the output of the counter; 1. An electronic timepiece equipped with a temperature compensation circuit, comprising: frequency adjustment means for adjusting the frequency of the reference signal in response to output data of a memory. 2. An electronic timepiece equipped with a temperature compensation circuit according to claim 1, wherein the read-only memory is activated in response to the output of the counter and outputs stored data.