JPS62123745A - Ceramic package type semiconductor device - Google Patents
Ceramic package type semiconductor deviceInfo
- Publication number
- JPS62123745A JPS62123745A JP60264327A JP26432785A JPS62123745A JP S62123745 A JPS62123745 A JP S62123745A JP 60264327 A JP60264327 A JP 60264327A JP 26432785 A JP26432785 A JP 26432785A JP S62123745 A JPS62123745 A JP S62123745A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- conductor layer
- ceramic
- semiconductor device
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係わシ、特に、セラミックパッケ
ージ型半導体装置のセラミック基板の形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the shape of a ceramic substrate of a ceramic package type semiconductor device.
近年、半導体素子の高集積化に伴ない、セラミックパッ
ケージの外部リード数も多ピン化が要求されるようにな
って来た。反面、高集積化の為、半導体素子自体の大き
さは、次第に小形になって来た。In recent years, as semiconductor devices have become more highly integrated, ceramic packages have been required to have a larger number of external leads. On the other hand, due to higher integration, the size of semiconductor elements themselves has become smaller and smaller.
このような半導体素子を搭載する多ビン半導体装置では
半導体素子と金属細線によって電気的に接続されるセラ
ミックパッケージの内部リードの幅、間隔とも１００．
ｍ程度もしくはそれ以下でなければ、半導体素子の周囲
、セラミック基板上に配置することが出来ない場合が多
くなってきた。In a multi-bin semiconductor device mounting such a semiconductor element, the width and spacing of the internal leads of the ceramic package, which are electrically connected to the semiconductor element by thin metal wires, are 100.
In many cases, it is not possible to arrange it around a semiconductor element or on a ceramic substrate unless it is about m or less.
このような、多ビン半導体装置としては、第５図、第６
図に示されているように、セラミック基板（以下グリー
ンシート）の平坦な表面にスクリーン印刷法を用い、金
属メタラズによる内部パターン２１を形成し、その後、
内部パターンを形成したグリーンシートの表面に平坦な
裏面を有する別のグリーンシート２２を積層し、その後
焼成して得られルＤＩＰ（Ｄｕａｌ Ｉｎ−１ｉｎｅ
）もしくはＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）タ
イプのセラミック積層型パッケージが広く用いられてい
る。Such multi-bin semiconductor devices are shown in FIGS. 5 and 6.
As shown in the figure, an internal pattern 21 of metal lath is formed on the flat surface of a ceramic substrate (hereinafter referred to as a green sheet) using a screen printing method, and then,
Another green sheet 22 having a flat back surface is laminated on the surface of the green sheet on which the internal pattern has been formed, and then fired to obtain a DIP (Dual In-1ine).
) or PGA (Pin Grid Array) type ceramic stacked packages are widely used.
近年の半導体素子の高積集化に伴ない、内部パターンの
幅、間隔は狭くならざるを得ないのに反し、内部パター
ンの厚さは積集度の向上に伴なう消費電力の増加、内部
パターンの導通抵抗の低下を防止する為、厚くする必要
が認められるようになって来た。As semiconductor devices have become more highly integrated in recent years, the width and spacing of internal patterns have become narrower. In order to prevent a decrease in the conduction resistance of the internal pattern, it has become recognized that it is necessary to increase the thickness.
しかしながら、上述した従来のＤｉＰ、ＰＧＡ等の積層
型セラミックパッケージでは、平坦なグリーンシートの
表面にスクリーン印刷法によジメタライズによる内部パ
ターンを形成し、その後平坦な裏面を有するグリーンシ
ートを積層して内部パターンを挾持していた為、内部パ
ターンの厚さが、厚くなるにつれ、内部パターン下部の
グリーンシートと上部のグリーンシート間の間隙３３が
太きくなシ、積層不良が発生するという問題点があった
。However, in the conventional multilayer ceramic packages such as DiP and PGA mentioned above, an internal pattern is formed by dimetallization on the surface of a flat green sheet using a screen printing method, and then a green sheet with a flat back surface is laminated to form an internal pattern. Since the pattern was sandwiched, as the thickness of the internal pattern becomes thicker, the gap 33 between the green sheet below the internal pattern and the green sheet above the internal pattern becomes thicker, resulting in a lamination failure. Ta.
本発明は、第１セラミック基板の表面と第２セラミック
基板の裏面とのいずれか一方または双方に導体層と同一
パターンの溝を形成し、第１セラミック基板に第２セラ
ミック基板を積層したとき、導体層が溝内に収納される
ようＫしたことを要旨とする。According to the present invention, when a groove having the same pattern as the conductor layer is formed on one or both of the front surface of the first ceramic substrate and the back surface of the second ceramic substrate, and the second ceramic substrate is laminated on the first ceramic substrate, The gist is that the conductor layer is accommodated in the groove.
以下に本発明の実施例を図面と共に説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例に係わるセラミック積層型パ
ッケージの断面図である。内部パターン１が形成される
セラミック基板２６は、内部パターン１が形成される以
前のグリーンシート状態において、メタライズによ多形
成される内部パターと略同−の深さの溝部３が形成され
る。その後メタライズによる内部パターンが溝部３に形
成する。FIG. 1 is a sectional view of a ceramic laminated package according to an embodiment of the present invention. In the ceramic substrate 26 on which the internal pattern 1 is formed, in a green sheet state before the internal pattern 1 is formed, a groove 3 having approximately the same depth as the internal pattern formed by metallization is formed. Thereafter, an internal pattern is formed in the groove portion 3 by metallization.
したがって、セラミック基板２ｂの上面は内部パターン
１、形成後においても平坦となるためセラミック基板２
Ｃを積層する際に積層不整が発生することを大幅に減少
することが出来る。Therefore, since the upper surface of the ceramic substrate 2b is flat even after the internal pattern 1 is formed, the ceramic substrate 2b
It is possible to significantly reduce the occurrence of lamination irregularities when laminating C.
また本発明に基づくセラミック積層型パッケージではセ
ラミック基板２ｂ上に形成する溝部３を深くすることに
よシ、内部パターン１の幅を増加させることなく導通抵
抗を低減出来る利点を有している。Furthermore, the ceramic laminated package according to the present invention has the advantage that conduction resistance can be reduced without increasing the width of the internal pattern 1 by deepening the groove 3 formed on the ceramic substrate 2b.
なお、溝３は第４図に示されているようにセラミック基
板２ａの表面部だけでなく、基板２ｂの裏面にも形成し
てもよく、基板２ｂの裏面にのみ形成してもよい。Note that the grooves 3 may be formed not only on the front surface of the ceramic substrate 2a as shown in FIG. 4, but also on the back surface of the substrate 2b, or may be formed only on the back surface of the substrate 2b.
以上説明してきたように、本発明によれば、導体膜が溝
内に収納されるので、第１セラミック基板の表面と第２
セラミック基板の裏面とが接触し、積層不良が生じない
という効果が得られる。As explained above, according to the present invention, since the conductive film is housed in the groove, the surface of the first ceramic substrate and the second
The back surface of the ceramic substrate comes into contact with the ceramic substrate, resulting in an effect that no lamination defects occur.
第１図は本発明の一実施例の断面図、第２図は第１図の
一部拡大斜視図、第３図は第２図の一部拡大図、第４図
は一実施例の変形例の一部拡大斜視図、第５図は従来例
の一部斜視図、第６図は第５図の一部拡大断面図である
。
１・・・・・・内部パターン、
２ａ、２ｂ・−・・・・セラミック基板、３・・・・・
・溝。
代理人 弁理士 内 原 晋
牟４ 図
第５ 凹 ヤ６凹Fig. 1 is a sectional view of one embodiment of the present invention, Fig. 2 is a partially enlarged perspective view of Fig. 1, Fig. 3 is a partially enlarged view of Fig. 2, and Fig. 4 is a modification of one embodiment. FIG. 5 is a partially enlarged perspective view of the example, FIG. 5 is a partially enlarged perspective view of the conventional example, and FIG. 6 is a partially enlarged sectional view of FIG. 1... Internal pattern, 2a, 2b... Ceramic substrate, 3...
·groove. Agent Patent Attorney Shinmu Uchihara 4 Figure No. 5 Ya 6
Claims (1)
パターン形成され半導体チップと電気的に接続される導
体層と、第１セラミック基板上に積層され該第１セラミ
ック基板と共に前記導体層を挾持する第２セラミック基
板とを有するセラミックパッケージ型半導体装置におい
て、前記第１セラミック基板の表面および第２セラミッ
ク基板の裏面のいずれか一方または双方に前記導体層と
同一パターンの溝を形成し該溝内に前記導体層を収納し
たことを特徴とするセラミックパッケージ型半導体装置
。a first ceramic substrate; a conductor layer patterned on the surface of the first ceramic substrate and electrically connected to the semiconductor chip; laminated on the first ceramic substrate and sandwiching the conductor layer together with the first ceramic substrate; In a ceramic packaged semiconductor device having a second ceramic substrate, a groove having the same pattern as the conductor layer is formed on one or both of the front surface of the first ceramic substrate and the back surface of the second ceramic substrate; A ceramic package type semiconductor device, characterized in that the conductor layer is housed therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60264327A JPH0727989B2 (en) | 1985-11-22 | 1985-11-22 | Method for manufacturing ceramic package type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60264327A JPH0727989B2 (en) | 1985-11-22 | 1985-11-22 | Method for manufacturing ceramic package type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62123745A true JPS62123745A (en) | 1987-06-05 |
| JPH0727989B2 JPH0727989B2 (en) | 1995-03-29 |
Family
ID=17401643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60264327A Expired - Lifetime JPH0727989B2 (en) | 1985-11-22 | 1985-11-22 | Method for manufacturing ceramic package type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727989B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04216654A (en) * | 1990-12-17 | 1992-08-06 | Kyocera Corp | Manufacture of package for accommodating semiconductor element |
| US5818108A (en) * | 1993-06-08 | 1998-10-06 | Alcatel N.V. | High-density, highly reliable integrated circuit assembly |
| US5907185A (en) * | 1996-09-24 | 1999-05-25 | Sumitomo Electric Industries, Ltd. | Ceramic terminal block, hermetic sealed package, and complex semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128663A (en) * | 1974-09-02 | 1976-03-11 | Nippon Electric Co | Denshikairoyokizai no seizohoho |
| JPS5878653U (en) * | 1981-11-24 | 1983-05-27 | 日本特殊陶業株式会社 | Ceramic package for mounting semiconductor elements |
-
1985
- 1985-11-22 JP JP60264327A patent/JPH0727989B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128663A (en) * | 1974-09-02 | 1976-03-11 | Nippon Electric Co | Denshikairoyokizai no seizohoho |
| JPS5878653U (en) * | 1981-11-24 | 1983-05-27 | 日本特殊陶業株式会社 | Ceramic package for mounting semiconductor elements |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04216654A (en) * | 1990-12-17 | 1992-08-06 | Kyocera Corp | Manufacture of package for accommodating semiconductor element |
| US5818108A (en) * | 1993-06-08 | 1998-10-06 | Alcatel N.V. | High-density, highly reliable integrated circuit assembly |
| US5907185A (en) * | 1996-09-24 | 1999-05-25 | Sumitomo Electric Industries, Ltd. | Ceramic terminal block, hermetic sealed package, and complex semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0727989B2 (en) | 1995-03-29 |
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