JPS6212596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an IC memory circuit, and more particularly to a memory circuit configured to transmit information of a memory cell from a digit line to an output circuit via a data bus line.

Conventionally, a method of transmitting signals from a digit line to a data bus line has been based on a circuit as shown in FIG. 1 or 2, for example. In Figure 1, Y ₁ , Y ₂ ...Y ₆₄ are the output terminals of the column decoder,
Q ₁₁ , Q ₁₂ , . . . Q ₆₄₁ , Q ₆₄₂ are insulated gate field effect (MIS) transistors having the digit line as the source, the data bus line as the drain, and the output terminal of the column decoder as the gate input. When the output Y _i of the selected one column decoder becomes the "1" level, Q _i1 and Q _i2 are turned on and the signal on the digit line is transmitted to the data bus line. Here, the transmission time is determined by the current capacity of Q _{i1 and} Q _i2 and the capacity of the data bus line, assuming that the current capacity of the cell and the capacity of the digit _line are given. The larger the data bus line is, and the smaller the capacity of the data bus line, the shorter the transmission time. By the way, if the dimension of Q _i1 and Q _i2 is increased in an attempt to increase their current capacity, the capacitance of the drain diffusion layer and the mirror capacitance between the drain and the gate increase. On the other hand, most of the capacity of the data bus line is Q _i
It consists of the drain diffusion layer capacitance of ₁ , Q _i2 and the mirror capacitance between the drain and gate. Therefore,
As described above, even if the current capacity of Q _i1 and Q _i2 is increased based on the above intention, the capacity of the data bus line increases, so it is difficult to shorten the transmission time.

In the second Q, Y ₁ , Y ₂ , ...Y ₆₄ are the output terminals of the column decoder, Q ₁₁ , Q ₁₂ , ... Q ₆₄₁ , Q ₆₄₂ have the digit lines as their respective sources, the data bus line as the drain, and the sources are common. This is a MIS transistor connected to the Q ₁₃ , . . . Q ₆₄₃ are MIS transistors having the above common point as a drain and the output terminal of the column decoder as a gate input. When the output Y _i of the selected one column decoder becomes the "1" level, Q _i3 is turned on, and the signal on the digit line is transmitted to the data bus line. Here, the transmission time can be reduced in appearance by increasing the dimensions of Q _i1 , Q _i2 , and Q _i3 . However, due to the coupling caused by the capacitances C ₁₁ , C ₁₂ , ...C ₆₄₁ , C ₆₄₂ that exist between the data bus line and the unselected digit line, noise in the opposite phase to the signal on the selected digit line is transmitted to the data bus line. , the effective signal transmission time does not become smaller. And this capacitance coupling is mainly Q ₁₁ , Q ₁₂ ,...Q ₆₄₁ ,
Since this is due to the Miller capacitance that exists between the drain and gate of Q ₆₄₂ , the noise increases as the dimension of Q _i1 and Q _i2 increases, and the circuit shown in this figure also has the same noise as the case in Figure 1. I end up in a dilemma.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory circuit which eliminates the above-mentioned drawbacks and quickly transmits signals from a digit line to a data bus line.

A memory circuit according to the present invention includes an amplifier circuit, first means for transmitting a signal on a digit line to an input terminal of the amplifier circuit, and second means for transmitting an output signal of the amplifier circuit to a data bus line. The circuit is characterized in that the amplifier circuit, the first means, and the second means are controlled by an output signal of a column decoder.

According to the present invention, a first MIS transistor has a first digit line connected to its source terminal and a column decoder output terminal connected to its gate terminal; a second MIS having a digit line connected to its source terminal and connected to the output terminal and gate terminal of the column decoder;
a transistor, an amplifier circuit in which drain terminals of the first and second MIS transistors are connected to first and second input terminals, respectively; and a first transistor of the amplifier circuit.
a third MIS transistor whose output terminal is connected to the source terminal and the output terminal of the column decoder is connected to the gate terminal; and a second output terminal of the amplifier circuit is connected to the source terminal and the output terminal of the column decoder is connected to the gate terminal. and a fourth MIS transistor connected to the gate terminal, and the drain terminals of the third and fourth MIS transistors are connected to a pair of data bus lines, respectively, and the amplifier circuit is connected to the first and fourth MIS transistors. a fifth MIS transistor having the second input terminal connected to the drain terminal and the gate terminal, respectively;
and a sixth MIS transistor, the first input terminal of which is connected to the drain terminal and the gate terminal, respectively; and the source terminals of the fifth and sixth MIS transistors are commonly connected to the drain terminal, and the first power source is connected to the source terminal. and a seventh MIS transistor connected to the column decoder and having the output terminal of the column decoder connected to the gate terminal.

The case of an N-channel MIS transistor will be explained below with reference to the drawings. FIG. 3 is a circuit diagram showing an embodiment of the present invention. In FIG. 3, when the output Yi of the column decoder rises after a signal appears on the digit line Di,i, the signal passes through the MIS transistors Q _i1 and Q _i2 to the MIS transistors Q _i3 and
It is transmitted to the amplifier circuit C _A composed of Q _i4 and Q _i5 . Y
The signal amplified by the amplifier circuit C _A controlled by the address decoder output Yi is transmitted to a pair of data bus lines DB through MIS transistors Q _i6 and Q _i7 . In this circuit, there is no capacitance between the digit line and the data bus line as in the conventional circuit shown in FIG. Therefore, signals on non-selected digit lines do not become noise and are not transferred to the data bus line. Next, in order to reduce the transmission time, it is sufficient to increase the dimension of Q _i5 , Q _i6 , and Q _i7 to increase the current capacity of the amplifier circuit C _A constituted by these MIS transistors. Furthermore, it is clear that in this case, the increase in the capacity of the data bus line, which occurs in the conventional circuit, does not occur.

As described above, the present invention greatly contributes to eliminating the drawbacks of conventional circuits and speeding up the transmission of signals from digit lines to data bus lines.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are circuit diagrams showing conventional circuits, respectively. FIG. 3 is a circuit diagram showing one embodiment of the present invention. Q ₁₂ , Q ₂₂ ... MIS transistor, Y ₁ , Y ₂ ...
Column decoder output terminal, C _A ...... amplifier circuit.

Claims (1)

[Claims] 1 a differential amplification circuit, a first pair of transfer gate means for transmitting signals on a pair of digit lines to a pair of input terminals of the amplification circuit, and a pair of data bus lines for transmitting an output signal of the amplification circuit; a second pair of transfer gate means is provided for each column, and a second pair of transfer gate means for transmitting a signal to the amplifying circuit and the first and second
and the transfer gate means are controlled by the output signal of the column decoder, and the amplifier circuit of the selected column is energized and the first and second transfer gate means are rendered conductive. memory circuit.