JPS621264B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a high voltage insulated gate field effect transistor (hereinafter referred to as an MIS transistor) and a method for manufacturing the same.

Generally, in semiconductor devices including MIS transistors, multiple transistors are formed on the same semiconductor substrate.
In order to prevent the element regions of MIS transistors from being connected by parasitic channels, a parasitic impurity of the same conductivity type as the semiconductor substrate but with a higher concentration is added to the semiconductor substrate surface directly under the field insulating film between these element regions. It is common to provide a channel prevention area. The reason is that by forming a parasitic channel prevention region, the threshold voltage of the MIS structure consisting of the semiconductor substrate, field insulating film, electrode wiring on the field insulating film, etc. can be increased. .

As a method for providing this parasitic channel prevention region, a method is known in which the parasitic channel prevention region is selectively formed in advance in a semiconductor substrate excluding element regions such as source, drain, and channel forming regions.

By the way, according to that method, later formed
There are cases where the source and drain regions of MIS transistors contact or partially overlap, and there is a problem that the junction breakdown voltage decreases especially in the drain region where high voltage is applied. Another problem has arisen in that separating the prevention region and the element region leads to a reduction in integration density.

In this regard, as shown in FIG. 1, a field insulating film 2 is selectively buried in a semiconductor substrate 1, a parasitic channel prevention region 3 is formed using the same mask as that used at this time, and then each MIS type transistor 4 is , 5, the degree of integration can be improved rather than reduced by the method of forming the source and drain regions 6, 7 and 8, 9 constituting the structure.
It is difficult to avoid overlapping of the source and drain regions and the parasitic channel prevention region.

Moreover, since the junction breakdown voltage and the threshold voltage of the field insulating film part have an inverse relationship with respect to the impurity concentration of the parasitic channel prevention region (that is, the higher the impurity concentration of the parasitic channel prevention region, the higher the threshold voltage of the field part However, in the opposite case, the rising and falling trends of the threshold voltage and junction breakdown voltage are reversed.) In the actual manufacturing of semiconductor devices, the desired threshold voltage, The impurity concentration in the parasitic channel prevention region must be selected and controlled to satisfy the junction breakdown voltage, and in some cases, the operating voltage range may be restricted due to the characteristics of the completed device. Ta.

Under these circumstances, there is an increasingly strong demand for miniaturization and higher integration of semiconductor devices, and in order to achieve this, there is a trend toward thinner insulating films formed on semiconductor substrates. Correspondingly, in order to prevent or increase the threshold voltage of the field portion, it is necessary to increase the impurity concentration in the parasitic channel prevention region, and in such a case, the above-mentioned problem of reduced junction breakdown voltage becomes even more obvious. It's starting to change.

Therefore, an object of the present invention is to realize the following items.

(1) To obtain an MIS type transistor that can maintain a high breakdown voltage regardless of the level of impurity concentration in the parasitic channel prevention region.

(2) To obtain a semiconductor device including an MIS type transistor that can be used under higher operating voltage.

(3) To obtain a semiconductor device including a high-voltage MIS type transistor that can improve integration density.

(4) To obtain a semiconductor device including various high-voltage MIS type transistors that can be used selectively depending on the required application.

(5) To obtain a semiconductor device in which a normal voltage (low voltage) MIS type transistor can be integrally formed without special isolation means from a high voltage MIS type transistor.

(6) Normal voltage MIS transistors and high voltage MIS
To provide a manufacturing method for easily integrating type transistors on the same semiconductor substrate.

The configuration of the present invention for achieving these objects is basically as follows.

1. A MIS transistor comprising a source region, a drain region, a gate insulating film on a channel region between the source and drain regions, and a gate electrode on the gate insulating film on the surface of a semiconductor substrate; In a semiconductor device in which a parasitic channel prevention region is formed,
The periphery of at least one of the source region or the drain region is surrounded by the gate portion or the gate portion and its extension, so that the source region or the drain region is separated from the parasitic channel prevention region by a distance substantially equal to the width of the gate portion or its extension. A semiconductor device characterized by:

2. A MIS transistor comprising a source region, a drain region, a gate insulating film on a channel region between the source and drain regions, and a gate electrode on the gate insulating film on the surface of a semiconductor substrate; In a semiconductor device in which a parasitic channel prevention region is formed,
The periphery of at least one of the source region or the drain region is surrounded by the gate portion or the gate portion and its extension, so that the source region or the drain region is separated from the parasitic channel prevention region by a distance substantially equal to the width of the gate portion or its extension. A semiconductor device, further comprising: further forming another MIS type transistor on the semiconductor substrate, and electrically connecting both transistors.

3. The semiconductor device according to item 2 above, wherein the further MIS type transistor is a depletion type transistor.

4. A method for manufacturing a semiconductor device including an MIS transistor, including (a) forming a parasitic channel prevention region in a predetermined pattern on the surface of a semiconductor substrate; (b) forming a pattern of the parasitic channel prevention region on the semiconductor substrate; Field insulation film is formed in almost the same pattern, thereby achieving high withstand voltage.
Step of defining an MIS type transistor formation region and a low breakdown voltage MIS type transistor formation region, (c) A laminated structure by sequentially forming an insulating layer and an electrode wiring material layer thinner than the field insulating film in both MIS type transistor formation regions. (d) a step of exposing, in the high-voltage MIS type transistor formation region, a portion where the source and drain regions are to be formed, partitioned by the laminated structure and surrounded by at least one side thereof; (e) exposing the portion where the source and drain are to be formed, which are partitioned by the laminated structure, in the low-voltage MIS transistor formation region; (f) forming the source and drain regions of each of the MIS transistors; A method for manufacturing a semiconductor device, comprising the step of introducing impurities into a planned portion of the surface of the semiconductor substrate to form source and drain regions of each MIS type transistor.

The present invention will be described below with reference to specific examples. More specific purposes included in the above purposes,
As well as detailed configurations for achieving the same are also made clear in those examples.

FIGS. 2A and 2B are a plan view and a cross-sectional view showing a high breakdown voltage MIS type transistor having a single configuration, which is the basis of the present invention.

On the surface of the semiconductor substrate 11 within the boundary 21 defined by the pattern of the field insulating film 12,
A MIS type transistor is formed. This MIS
The type transistor consists of P ⁺ type source and drain regions 13 and 14, a gate insulating film 15 on the channel region between the source and drain regions, and a gate electrode 16 thereon, and 17 and 18 are interlayer insulating layers, respectively. These are source and drain electrode wirings provided through the film 19. A parasitic channel prevention region 20 having a higher impurity concentration than the semiconductor substrate 11 is provided below the field insulating film 12 (FIG. 2B).

What should be noted here is that, as shown in FIG.
It has a portion 24 that extends not only over the channel region between the regions 4 and 4 but also extends from the boundary 21 into the element formation region and surrounds the drain region. This portion 24 is an integral structure continuous from the gate portion 23 constituted by the gate insulating film 15 and the gate electrode 16, and is an extension of the gate portion 23.

Here, if silicon or the like is used as the gate electrode wiring material and patterned, the source and drain regions are formed, for example, in self-alignment, by diffusion or the like, so that the drain region exists directly below the extension portion 24. Drain region 1
4 and the parasitic channel prevention region 20 are completely eliminated.

Therefore, with such a structure, the periphery of the drain region 14 is separated from the parasitic channel prevention region, so that a high breakdown voltage can be obtained regardless of the impurity concentration of the parasitic channel prevention region 20.

Drain region 14 and parasitic channel prevention region 2
0 is the extension part 2 of the gate part 23.
4. If there is lateral diffusion in both regions directly below the area, the width will tend to be somewhat shorter, but if the width d of the extension part 24 is designed to be larger than the expected lateral diffusion width, it will almost become shorter. d.

The magnitude of d can be set depending on the magnitude of the voltage that can be applied to the drain region 24, taking into consideration the extension of the depletion layer.

Although FIG. 2 shows a case in which the drain region 14 is surrounded by the gate portion 23 and its extension portion 24, based on the concept of separating the drain region from the parasitic channel prevention region, it is possible to surround the drain region by only the gate portion. It may be configured to surround the drain region.

That is, it has a structure in which a drain region is surrounded by a gate part, and further surrounded by a gate part and a source region, as shown in _Q2 in FIG. 5, which will be described later. In this case, the source region comes into contact with the parasitic channel prevention region, but since high voltage is generally not often applied to the source region, there is little risk of a drop in breakdown voltage.

However, when a MIS type transistor is used bidirectionally or in other cases where a high breakdown voltage is required also in the source region, the above-mentioned means for achieving a high breakdown voltage ratio can be applied as is.

The conduction type of the MIS type transistor having the structure disclosed herein may basically be either an enhancement type or a depletion type. However, when the structure shown in the figure takes a depletion type, the semiconductor substrate 11 between the source and drain regions 13 and 14
At the stage of forming the depletion channel region on the surface, it is necessary to prevent impurity doping into the surface of the semiconductor substrate immediately below the extension 24. Although the field insulating film 12 is shown partially embedded in the semiconductor substrate 11 in FIG. 2, as is clear from the above, this is not an essential requirement of the present invention, and other flat materials may be used. Needless to say, it may be formed on a semiconductor substrate.

Figures 3a and 3b show that the high-voltage MIS transistor described in connection with Figure 2 is connected to another MIS transistor, and both transistors are combined into a single transistor.
It shows a structure that aims to achieve high voltage resistance when viewed as an MIS type transistor.

In this example, MIS type transistors Q ₁ , Q ₂ , and Q ₃ are formed in element formation regions within boundaries 42 and 43 of field insulating film 32 formed on the surface of N ^- type semiconductor substrate 31, respectively. Q ₁ and Q ₂ form the high-voltage section, and Q ₃ forms the normal-voltage (low-voltage) section.

As is clear from figure a, the gate electrode wiring 4
4 has a gate portion 45 of Q ₁ and a gate portion 46 of Q ₂ , and is further continuous to an extension portion 47 of the gate portion 46.

This extension 47 is formed so as to extend to the element formation region inside the boundary 42, as in FIG.

In addition, _{in FIG} .
(This region is also the drain region of Q ₁ , and Q ₁ , Q ₂
), the drain region 35, and the gate insulating film 36 and gate electrode 37 having the same structure as the gate part of _Q1 , and the drain electrode wiring 39 is drawn out through the interlayer insulating film 40. It shows. The source electrode wiring is also connected to the source region 33 via an interlayer insulating film 40, as shown in FIG.

The device regions 33, 34, and 35 are formed in self-alignment with respect to the gate portions 45, 46 and the extension portion 47.

According to this structure, the peripheral part of the drain region 35 to which a high voltage is applied is the parasitic channel prevention region 4.
Since there is no contact with Q 1 at all, a high _withstand voltage can be obtained as explained with reference to FIG.
Q _2The overall withstand voltage can be increased.

An equivalent circuit of this structure is shown in FIG. 6a. According to the figure, MIS type transistors Q ₁ and Q ₂ have their gates connected in common, and the source side of Q ₁ is connected to the reference potential GND. When configuring a logic circuit or the like using these transistor configurations, a load MIS type transistor is connected to the drain side of _Q2 , and it is connected to a high potential point such as a power supply potential. As a result, Q ₁ and Q ₂ operate as driver transistors of the inverter circuit.

In this configuration, a higher withstand voltage can be obtained if Q ₂ is a depletion type. The reason for this is that in the case of the depletion type, since a channel region is formed in advance, it is possible to promote the extension of the depletion layer from the drain region 35 when a high voltage is applied to the drain region 35, and to keep the channel region in a conductive state. This is because the voltage applied to the intermediate region 34 can be lowered to some extent due to the voltage drop due to the resistance component in the channel region.

In Figure 3, Q ₁ and Q ₂ are made to coexist in the same element formation area, but in terms of design, each transistor is formed in a separate element formation area and the necessary electrical connections are made. Good too.

FIG. 4 shows still another embodiment of the present invention, in which parts common to those in FIG. 3 are given the same reference numerals.

This structure is basically different from the structure shown in FIG. 3 because the gate part 48 of _Q2 and its extension part 49 are
Q ₁ is independent from the gate portion 45 and its electrode wiring 44 and is connected to the drain region 35 .
Although the gate portion 48 is illustrated as partially staying inside the element formation region, its expansion may reach the top of the field insulating film 32, and this is not an essential matter. For applications in which it is desired not to reduce the drain current I _D as a composite characteristic of Q ₁ and Q ₂ , it is desirable to form the gate portion 48 only within the boundary 42 as shown in FIG. 5a, which will be described later.

The equivalent circuit of this structure is as shown in Figure 6b,
Q _L may be further connected to the connection between Q ₁ and Q ₂ as a load, or if Q ₂ is an enhancement type, Q ₂ itself can be used as a load without Q _L.

Now, let's look at the case where Q ₂ is formed as an enhancement MIS type transistor.
Since the peripheral portion of the drain region 35 does not come into contact with the parasitic channel prevention region 41, a correspondingly high breakdown voltage can be obtained. In addition, when Q ₁ is non-conducting or about to become non-conducting, the potential of the source region 34 of Q ₂ rises, causing the apparent threshold voltage of Q ₂ to drop to the true threshold according to its reverse bias. As a result, the potential appearing in the intermediate region 34 is lower than the voltage applied to the drain region 35 by the above-mentioned apparent threshold voltage, and
Since a voltage drop occurs due to the resistance component in the channel region of Q ₂ , the voltage applied to the intermediate region 34 can be made considerably smaller than the value applied to the drain region 35. voltage).

However, when Q ₁ and Q ₂ are integrated into a single transistor,
When extracting the output from between Q ₂ and Q _{L of
Combined} drain current − drain voltage (I _D −
Since the V _D ) characteristic curve shifts by the threshold voltage of Q ₂ , the voltage value at the low output level becomes higher and the noise margin becomes smaller, so it is desirable to use it selectively depending on the application.

Further, when Q ₂ is formed as a depletion type, a high breakdown voltage can be obtained for the same reason as explained in FIG. 3.

When Q ₂ is of the depletion type, there is no shift in the I _D -V _D characteristic as in the enhancement type described above, so there is no decrease in the extraction force amplitude.
Suitable for applications that require a large noise margin.

It is also possible to connect a plurality of MIS type transistors _Q2 as shown in FIG. 4, and in this case, a semiconductor device with higher breakdown voltage can be obtained.

In this embodiment, since the drain electrode wiring 39 can be taken out across the extension part 49, there is an advantage that the electrode can be taken out without precise mask alignment.

As a modification of the embodiment shown in FIG. 4, it is also possible to connect the gate of Q ₂ directly to the power supply voltage V _D or another suitable high potential point without passing through the load transistor Q _L , as shown in FIG. 6 c. be. In this case, Q ₂ can be formed in the enhancement form, and also the above I _D
It is also possible to eliminate shifts in the −V _D characteristics.

FIG. 5 shows a suitable structural example in which Q ₂ is formed as a depletion type. The gate electrode of the gate portion 48 of Q ₂ is connected to its source region 34 .

With this configuration, the drain region 3 of _Q2
Regarding No. 5, in addition to the fact that its peripheral portion is completely separated from the parasitic channel prevention region 41, the potential of the source region 34 is applied to the gate portion 48, which facilitates the extension of the depletion layer from the drain region 35. Because of this, the withstand voltage is significantly improved.

Further, as the potential of the source region 34 increases, the substrate bias effect forces Q ₂ into a pinch-off state, so the potential of the source region 34 is clamped to the potential at the pinch-off state.

Therefore, even if any voltage in the range below the withstand voltage of the drain region 35 is applied to the drain region, the source potential always maintains the current at the pinch-off time, so there is a relationship that the voltage at the pinch-off time is smaller than the withstand voltage of the source region 34. By maintaining , it can withstand use under higher power supply voltage.

In order to maintain the above relationship, the true threshold voltage V _thi of Q ₂ and the threshold voltage increase △V _th due to the body bias effect should cancel each other out (V _thi - △V _th = 0). (This is derived from the generally known formula for calculating the apparent threshold voltage due to the substrate bias effect and the relational formula for drain current-conductance-threshold voltage, etc.).

Here, △V _th is the substrate effect coefficient K (determined by the gate insulating film thickness, impurity concentration of the semiconductor substrate, etc.)
Since this is a function of the pinch-off voltage, if the pinch-off voltage is set to be less than the withstand voltage of the source region 34, △V _thi - △V _th = 0 is a function between the value of V _thi itself and the value of K. This will be achieved through the coordination of

Adjusting the K value has a large impact on overall device design, so in reality, adjusting the K value by ion implantation, etc.
ΔV _thi control, which is independent of the value, is considered to be an easier method to select.

However, if V _thi is decreased, the drain current value decreases under normal operating conditions, so if the degree of decrease becomes a problem, as shown in Figure 5a,
It is sufficient to form the gate portion 48 of Q ₂ so as to fit completely inside the boundary 42 . This is because the conductance β can be increased.

The equivalent circuit of this structure is as shown in Figure 6d,
Q ₂ may also be used as a load, or another MIS type transistor Q _L may be connected as a load.

Further, by forming Q ₁ and Q ₂ in separate element forming regions and electrically connecting them, it is also possible to obtain a structure as shown in FIG. 6d.

Furthermore, if it is desired to realize a high-voltage MIS type transistor configuration that can obtain a high output voltage while using a high power supply voltage, Q _L in FIG. The gate electrode may be connected to the drain region side of Q _L , that is, to the power supply voltage V _D side, so that the output can be taken out between Q ₂ and Q _L.

The output voltage at this time is the difference voltage between the power supply voltage V _D and the apparent threshold voltage of Q _L. As mentioned above, the magnitude of this apparent threshold voltage is determined by the true threshold voltage V _thi of Q _L and the threshold voltage change △V due to the body bias effect.
It is determined by the relationship with _th , but when the K value is about 0.5, |V _thi |
When is about 2V, it is possible to keep it within 10% of the power supply voltage. MIS type transistors that can be used in such a voltage drop range can be either enhancement type or depletion type, and depletion type is particularly advantageous because it can reduce the apparent threshold voltage.

As explained above, according to the present invention, a semiconductor device with excellent breakdown voltage can be obtained through various configurations thereof.

For example, in a high voltage MIS transistor configured as shown in FIG. 5, the gate oxide film thickness t _px = 1000
Å, field oxide film thickness T _px = 1.2 μ, impurity concentration of semiconductor substrate C _B = 1×10 ¹⁵ atoms/cm ² , impurity concentration of source and drain regions N _A = ~1×10 ²⁰
atoms/cm ² , impurity concentration in the parasitic channel prevention region of the field portion N _F = ~3×10 ¹⁶ atoms/cm ³ (phosphorus ion implantation 6×10 ¹² atoms/cm ³ ) V _thi of Q ₂ = 2V
As a result, the threshold voltage of the field section V _thF = 50V, and the drain region breakdown voltage B _VD =
Characteristics of 50V, source region breakdown voltage B _VS ≒20V, |source region potential | 16V were obtained, confirming that it can be used at high power supply voltages up to 50V.

On the other hand, for MIS transistors made under the same conditions and without any countermeasures, the maximum usable power supply voltage was about 25V (V _thF = B _VD = B _VS = 25 V). .

As described above, the characteristics of the MIS type transistor according to the configuration of the present invention are significantly improved compared to those without the configuration.

Further, by connecting a plurality of MIS type transistors _Q2 , a semiconductor device with higher breakdown voltage can be obtained.

Furthermore, in the present invention, the breakdown voltage of the MIS transistor can be set regardless of the impurity concentration in the parasitic channel prevention region, so it is also possible to increase the impurity concentration and reduce the area occupied by the field insulating film. Furthermore, since the thickness of the field insulating film itself can be reduced to enable microfabrication, a highly integrated semiconductor device can be realized.

FIG. 7 shows an example of a manufacturing method for obtaining the semiconductor device shown in FIG. 5 in order of steps.

(a) A thermal oxide film (SiO 2 ) 72 with a thickness of 800 Å is formed on the surface of an N ^- type semiconductor substrate 71 with a specific resistance of 5 to 8 Ω-cm on the (100) plane, and a 1400 Å thick thermal oxide film (SiO ₂ ) 72 is formed on this SiO ₂ film 72. A nitride film (SiN) 73 is formed. Then, a photoresist film 74 with a thickness of 8500 Å is formed on this SiN film 73, and this photoresist film is selectively exposed and etched. Using this photoresist film 74 as a mask, the SiN film 73 and the SiO ₂ film 72 are selectively etched to form a window for forming a parasitic channel prevention region. In this state, phosphorus ions are implanted into the exposed surface of the semiconductor substrate 71 in an amount of about 2 to 5×10 ¹² atoms/cm ² to form a parasitic channel prevention region 75 . This parasitic channel prevention region does not come into contact with the drain region that will be formed in a later step.
Here, the ion implantation concentration can be increased arbitrarily depending on the magnitude of the desired threshold voltage of the field portion.

(b) Remove the photoresist film 74 and remove the SiO ₂ film 72.
and the semiconductor substrate 7 using the SiN film 73 as a mask.
The exposed surface of No. 1 is selectively oxidized. This selective oxidation is carried out at a temperature of 1000℃ in a mixed atmosphere of oxygen and water vapor.
It lasts about 7 hours. This results in a thickness of approximately 1.2
A thick buried oxide film (SiO ₂ film) 76 of μ is formed. Further, a parasitic channel prevention region 75 with an impurity concentration of about 10 ¹⁶ to 10 ¹⁷ atoms/cm ³ exists directly below this SiO ₂ film 76 . This parasitic channel prevention region and the SiO ₂ film 76 are self-aligned and formed using the same mask.

(c) Etching and removing the SiN film 73 and removing the SiO ₂ film 72
I'll leave it there. A portion of this SiO ₂ film 72 is to be used later as a gate oxide film. Alternatively, the flat SiO ₂ film 72 may be removed and a new clean oxide film (SiO ₂ film) formed.

A polycrystalline silicon layer 77 with a thickness of 3500 Å is formed over the entire surface of the semiconductor substrate 71 at 600° C. in a mixed atmosphere of nitrogen and silane (SiH ₄ ).

(d) This polycrystalline layer 77 is selectively etched using the photoresist layer as a mask, and then the SiO ₂ film 72 is removed by etching using the polycrystalline layer as a mask. The pattern at this time is such that the gate insulating film 78 and the gate electrodes 79, 80 and 81, 82 and 83 constitute independent gate parts, and the gate insulating film 80 and gate A gate portion consisting of an electrode 81 is formed to surround it.

After that, using each gate portion and the SiO ₂ film 76 as a mask, an impurity concentration of 10 ²⁰ is added into the N ^- type semiconductor substrate 71.
Boron, a P-type impurity, is diffused at a temperature of 1000°C for about 30 minutes to a concentration of atoms/cm ³ to form the source and drain regions 84 and 85 of MIS transistors that constitute the high breakdown voltage section and the normal breakdown voltage (low breakdown voltage) section. ,8
6, 87 and 88 are simultaneously formed in self-alignment.

At this time, each gate electrode 79, 81 and 83
Since it is also heavily doped with P-type impurities, it has low resistance and can be used as electrode wiring.

(e) An interlayer insulating film (phosphorus silicate glass: PSG) 84 with a thickness of approximately 7000 Å is formed on the entire surface of the semiconductor substrate 71, and a portion of the source and drain regions of each MIS transistor is exposed using the photoresist layer as a mask. Then, electrode wiring layers (aluminum layers) connected to each region are formed through these windows, and finally a semiconductor device as shown in FIG. 5 is obtained.

As is clear from the above, according to the manufacturing method of the present invention, a high voltage MIS transistor and a normal voltage MIS transistor can be integrally formed on the same semiconductor substrate in a completely compatible process without any additional process. can.

Also, parasitic channel prevention area and embedded _SiO2
Since the film, gate region, source and drain regions are formed in self-alignment with each other, masking and
There is no need to repeat etching, etc., and in addition to reducing the number of steps, it is possible to achieve a high degree of integration.

Furthermore, since the impurity concentration for forming the parasitic channel prevention region can be controlled arbitrarily, miniaturization corresponding to an increase in concentration can be achieved, thereby promoting higher integration.

As described above, the manufacturing method of the present invention is a process that is suitable for process simplification, and has great industrial value in terms of yield improvement, integration degree improvement, cost reduction, etc.

The present invention can be applied, for example, to a case where an output signal from a normal withstand voltage circuit section as shown in FIG. 8 is outputted under a high voltage power supply. Since the magnitude of the threshold voltage of can be increased independently,
Even when integrated on the same semiconductor substrate, if the threshold voltage of the field section is set high, it is possible to arrange MIS type transistors in circuit sections with different withstand voltages close to each other.

Furthermore, if the high voltage structure of the present invention is applied to the MIS type transistor in the normal voltage circuit section,
Integration is possible without means for isolating the high voltage circuit section and the normal voltage circuit section or for protecting the normal voltage circuit section.

These are the MIS components that make up both voltage-resistant circuits.
This shows that it is possible to integrate and form transistors with a high degree of integration.

Furthermore, the latter case also has the advantage that the power supplies V _D and V _H of different voltages in the normal voltage circuit section and the high voltage circuit section can be unified into a single power source.

In a circuit like the one shown in Figure 8, the depletion type
When applying a high breakdown voltage structure as shown in Fig. 5, which is explained as a preferred example using MIS transistors, the breakdown voltage of the constituent transistors is not affected at all even when a high power supply voltage is used in the normal breakdown circuit section. It ensures low-voltage drive without any voltage disturbance, and also guarantees high-voltage output operation approximately close to the power supply voltage used in the high-voltage circuit section, so it can meet the wide-ranging demands for higher voltage resistance in practice.

Although each embodiment of the present invention has been described using a P-channel MIS transistor, the present invention can be similarly applied to an N-channel MIS transistor or both types of CMOS MIS transistors.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device including an MIS transistor, FIGS. 2 a and b are a plan view and a sectional view, respectively, of the MIS transistor of the present invention, FIGS. 3 a, b, and 4 a, b. 5a and 5b are diagrams each showing an embodiment of a semiconductor device including an MIS type transistor of the present invention, where each a is a plan view and each b is a sectional view. Figures 6a, b, c, and d show circuit diagrams of MIS type transistors, and Figures 7a, b, c, d, and e show an embodiment of the method for manufacturing a semiconductor device including the MIS type transistor of the present invention. Cross-sectional diagram for each process, No. 8
The figure is a circuit diagram of an integrated semiconductor device as an example to which the present invention can be applied. 1, 11, 31, 71...N ^- type semiconductor substrate,
2, 12, 32, 76...field insulating film,
3, 20, 41, 75... N-type parasitic channel prevention region, 4, 5, Q ₁ , Q ₂ , Q ₃ , Q _L ... MIS type transistor, 6, 7, 8, 9, 13, 14, 3
3, 34, 35, 84, 85, 86, 87, 88
...P ⁺ type source and drain regions, 17, 18,
38, 39...source, drain electrode wiring, 1
9, 40, 89...Interlayer insulating film, 15, 36, 7
8, 80, 82...gate insulating film, 16, 37,
79, 81, 83...gate electrode, 22, 44...
...Gate electrode wiring, 23, 45, 46, 48...
Gate part, 24, 47, 49... Extension part of gate part, 21, 42, 43... Boundary, 72... SiO ₂
Film, 73... SiN film, 74... Photoresist film.

Claims (1)

[Scope of Claims] 1. A gate portion comprising a source region, a drain region, a gate insulating film on a channel region between the source and drain regions, and a gate electrode on the gate insulating film on the surface of a semiconductor substrate. Become
In a semiconductor device in which an MIS type transistor and a parasitic channel prevention region are formed, at least one of the source region and the drain region is surrounded by the gate portion or the gate portion and an extension thereof. or a semiconductor device separated from the parasitic channel prevention region by a distance approximately equal to the width of the extended portion thereof. 2. Consists of a source region, a drain region, a gate insulating film on a channel region between the source and drain regions, and a gate electrode on the gate insulating film on the surface of the semiconductor substrate.
In a semiconductor device in which an MIS type transistor and a parasitic channel prevention region are formed, at least one of the source region and the drain region is surrounded by the gate portion or the gate portion and an extension thereof. Alternatively, a semiconductor device characterized in that another MIS type transistor is formed on the semiconductor substrate, separated from the parasitic channel prevention region by a distance approximately equal to the width of the extended portion thereof, and both transistors are electrically connected. 3. The semiconductor device according to claim 2, wherein the further MIS type transistor is a depletion type transistor. 4. A method for manufacturing a semiconductor device including an MIS transistor, including (a) forming a parasitic channel prevention region in a predetermined pattern on the surface of a semiconductor substrate; (b) forming a pattern of the parasitic channel prevention region on the semiconductor substrate; (c) forming a field insulating film in almost the same pattern, thereby defining a high voltage MIS transistor formation region and a low voltage MIS transistor formation region; (c) forming a field insulation film in both MIS transistor formation regions; a step of sequentially forming a thin insulating layer and an electrode wiring material layer to form a laminated structure; (e) exposing the surrounded source/drain region forming area; (e) exposing the source/drain forming area partitioned by the laminated structure within the low-voltage MIS transistor forming area; (f) A semiconductor characterized by including the step of introducing impurities into the surface portion of the semiconductor substrate in the portion where the source and drain regions of each of the MIS type transistors are to be formed to form the source and drain regions of each of the MIS type transistors. Method of manufacturing the device.