JPS62140184A - local image processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital image processing device, and more particularly to a local processing type image processor.

2. Description of the Related Art In general, digital image processing deals with two-dimensionally arranged image data, and is one of the types of arithmetic processing that current sequential computers are not good at. Further, image processing requires a large amount of calculation time and storage capacity. Therefore, various image processors have been proposed to speed up image processing.

Among various image processors, local processing type image processors (hereinafter referred to as local image processors) are the most commonly developed because they allow relatively easy configuration of image processing systems. The present invention is also similar to this local image processor, and the conventional local image processor will be described below.

In general, a local image processor extracts local area data of a certain appropriate size from input image data and performs calculations on this local area data. It performs image processing.

Many image operations are performed using local processing, such as averaging, differential operations, and feature extraction.The complexity of these processings varies depending on the shape and size of the local region, but in general, 3x3
Image processing is performed on a local area of about 16×16. FIG. 4 shows an example of a conventional local image processor.

Figure 4 is an example of 3x3 local processing;
'J-1m Input image divided into Xn pixels, 2°3 each being a 7-foot register of n bits.

21 is a local image processor that performs local image processing;
4 to 12 are 1-bit shift registers, 14 to 16 are image data input terminals, 17 to 19 are image data output terminals,
13 is an arithmetic unit, and 20 is an arithmetic result output terminal.

Image data is successively extracted pixel by pixel by scanning from one input screen and transferred to the soft register 4. In addition, the second n-bit shift register in the shift register 7 transfers data that is delayed by one line with respect to the data transferred to the shift register 4. Similarly, data delayed by two lines is transferred to the shift register 1o by the second and third n-bit shift registers.

As described above, pixel data delayed by one line is sent to shift registers 4, 7.10, and shift registers 4, 7.
Image data is transferred pixel by pixel from 10 to shift registers 5, 8.10, respectively, and from 11 to 6, 9.12, respectively.

Through the operations described above, the pixel data taken out one pixel at a time from the input image is reconfigured by the shift registers 4 to 12,
It can be sequentially extracted as local area data in a 3×3 neighborhood. (These shift registers 4 to 12 are referred to as local area registers.) As described above, the calculation unit
3, image processing of the entire screen can be performed by sequentially performing signal processing.

Generally, when implementing such a local image processor into an integrated circuit, the size of the integrated circuit is limited to 3x3 to 6
×6 local area has been realized. Therefore, a plurality of local image processors are used to perform local image processing on an expanded wide area. 3x3 in Figure 6
A case is shown in which 6×6 extended local image processing is performed using four local image processors each having local area registers. 3
Reference numeral 7 designates an image signal input terminal, and 2, 3 and 3o to 32 designate shift registers for delaying one line, from which image data for six upstream lines can be taken out at the same time.

21-1 to 21-4 are local image processors shown in FIG. 4, 21iC, and terminals 14 to 20 correspond to terminals with the same numbers shown in FIG. By connecting the image data output terminal of the local image processor 21-1.21-3 to the image data input terminal of the local image processor 21-2.21=4 as shown in the figure, the target The pixels of the extended local area (6×6 pixels in the figure) are simultaneously taken into each of the local image processors 21-1 to 21-4.

In FIG. 6, 40 is the screen to be processed;
1.42, 43.44 are local image processors 2, respectively.
1-4.21-3.21-2.21-1 show local areas that are captured simultaneously at arbitrary timings. In this way, in the conventional local image processor configuration that allows expansion of the local area to be processed, this expanded local area is simultaneously taken into multiple local image processors, so calculations such as spatial sum of products over the entire expanded local area are performed. When performing this, local image processors 21-1 to 21-4 are used as shown in FIG.
It was necessary to add the outputs 20 obtained by performing spatial product-sum operations on 3×3 pixels in the arithmetic unit 200 using external adders 33 to 35.

Problems to be Solved by the Invention In such a conventional configuration, when a plurality of local image processors are used to perform local area expansion processing, an external adder is required, making the configuration complicated.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a local image processor with a local area register having one bit more in the horizontal direction than the local area to be processed, and an arithmetic unit having an external data input terminal. It consists of:

Effect of the Invention With the above-described configuration, the present invention is configured such that when a local area expansion process is performed using a plurality of local image processors, the calculation output signal of each local image processor is arranged at the next stage in the scanning direction of the local area. By connecting to the data input of a local image processor and performing operations in the arithmetic unit on the pixel data and data input of the local area to be processed, processing such as spatial product-sum operations can be performed using an external adder. It can be executed without using .

Embodiment FIG. 1 is a block diagram showing an embodiment of the local image processor of the present invention. Components in FIG. 1 that are the same as those in FIG. 4 are designated by the same numbers.

1 is an input image, 2 and 3 are one-line delay registers, and 21 is a local image processor. Reference numerals 4 to 12 are 1-bit shift registers, which, together with registers 2 and 3, take in data of target local area pixels. 13
is an arithmetic unit, which receives local area pixel data taken out by 4 to 12 shift registers and data input terminal 2.
The calculation is performed on the external input data of No.6. 22-24 are 1-bit shift registers, which add 1 bit in the horizontal direction to the local data registers 4-12. 1
4 to 16 are local image data input terminals, 17 to 19 are local image data output terminals, and 20 is a calculation result output terminal.

By adding the shift registers 22 to 24 in this way, when performing expanded local area image processing, the output signals of the image data output terminals 17 to 19 sent to the next stage become signals delayed by one pixel. FIG. 2 shows a case where a plurality of local image processors 21 shown in FIG. 1 are used to perform image processing on a busy local area. Components in FIG. 2 that are the same as those in FIG. 5 are designated by the same numbers.

37 is an image signal input terminal, 2, 3 and 30 to 32 are 1
This is a line delay shift register, which allows six lines of image data to be taken out at the same time.

21-1 to 21-4 are local image processors shown in FIG. 1, and terminals 14 to 20 and 21 correspond to terminals with the same numbers shown in FIG. As shown in the figure, the image data output terminal of the local image processor 21-1.21-3 is connected to the image data input terminal of the local image processor 21-2.21-4, and the shift register 3 and shift register 30 are connected to each other. By inserting a 2-bit shift register 38 in between, each local image processor 21-1 to 21-
The pixels of the local area captured at arbitrary timing in 4 are as shown in FIG. In FIG. 3, 40 is a screen to be processed, and 41, 42, 43, and 44 are local image processors 21-4, 21-3, 21-2, respectively.
．． 21-1 at the same time at an arbitrary timing. As shown in the figure, each local image processor 21
-Local image areas 41 to 44 captured in 1 to 21 to 4
There is an interval of 1 pixel in the horizontal direction and 2 pixels in the vertical direction, and as shown in Fig. 2, each local image processor 2
The output signals of the calculation result output terminal 20 of 1-1 to 21-4 are sent to the data input terminal 25 of the next-stage local image processor in the scanning direction of the local area, and in spatial product-sum calculations, etc. The product-sum calculation result for the target local area is summed with the product-sum calculation result for the target local area in the next stage at the next timing.

In this way, by sequentially transferring the calculation results of each local image processor in the scanning direction of the local image area, the target extended local area ( In the case of the figure, a calculation result of 6×6) can be obtained.

Note that the number of bits of the shift register 38 shown in FIG. 2 changes depending on the number of local image processors used for extended local area processing.

Effects of the Invention As described above, according to the present invention, local area expansion processing can be realized with a simple configuration by simply expanding the local area register by 1 bit in the horizontal direction, and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a local image processor in an embodiment of the present invention, FIG. 2 is a block diagram of an apparatus that performs extended local processing using a plurality of local image processors in this embodiment, and FIG. Figure 4 shows the processing area of each local image processor in extended local processing by the apparatus in Figure 2;
This figure is a block diagram of a conventional local image processor, FIG. S is a block diagram of a conventional extended processing device, and FIG. 6 is a diagram showing the processing area of each local image processor in extended local processing. 4 to 12--Local area register, 13...
- Arithmetic unit, 21...Local image processor, 22-24...Shift register. Name of agent: Patent attorney Toshio Nakao and 1 other person 4-
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- Schiff F L >'En'7 Figure 2 Figure 5

Claims (1)

[Claims] A local area register that takes in pixel data of a local image area to be processed and an arithmetic unit that performs an operation based on the pixel data, and is expanded by one pixel in the horizontal direction with respect to the local image area to be processed. a local area register; and an external data input terminal provided in the arithmetic unit.