JPS62142402A - frequency modulator - Google Patents

frequency modulator

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Publication number
JPS62142402A
JPS62142402A JP60283537A JP28353785A JPS62142402A JP S62142402 A JPS62142402 A JP S62142402A JP 60283537 A JP60283537 A JP 60283537A JP 28353785 A JP28353785 A JP 28353785A JP S62142402 A JPS62142402 A JP S62142402A
Authority
JP
Japan
Prior art keywords
phase
integrator
bits
frequency
word length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60283537A
Other languages
Japanese (ja)
Inventor
Hideki Otaka
秀樹 大高
Shiro Kato
加藤 士郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60283537A priority Critical patent/JPS62142402A/en
Publication of JPS62142402A publication Critical patent/JPS62142402A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To contrive to compact the scale of the circuit by providing an integra tor and a phase amplitude converter that outputs sine values or cosine values making output of the integrator input and lengthen a word length of the integra tor longer by at least more than 1 bit than an input word length of phase angle of the phase amplitude converter in lower direction. CONSTITUTION:A constant C (product of carrier angle frequency omegaC and sam pling period T) is added by an adder 2 to digital modulated signals inputted to a terminal 1, and the result of addition is inputted to an integrator 5 consisting of an adder 3 and a delay unit 4. Phase angle theta is calculated by the integrator 5, and the output of the integrator 5 is inputted to an amplitude phase converter 6. here, the word length of the integrator 5 is made N bits and the word length of the phase amplitude converter 6 is made N-1 bits made by reducing the lowermost bit of the integrator 5 by 1 bit. Thus, when FM modulating and demodulating inputted modulated signals expressed by proper number of bits at gradation of N bits, if frequency of a modulation signal is low, the amplitude of signals of unnecessary frequency is small, and the specific frequency component is attenuated by a low-pass filter, and accord ingly, the gradation of N bits is obtained in demodulating side.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、周波数変調装置に関する。[Detailed description of the invention] Industrial applications The present invention relates to a frequency modulation device.

従来の技術 以下に従来の周波数変調装置(FM変調装置)の例を示
す。
BACKGROUND OF THE INVENTION An example of a conventional frequency modulation device (FM modulation device) is shown below.

一般に変調信号をV(t)、搬送波の中心角周波数2、
、。
Generally, the modulation signal is V(t), the center angular frequency of the carrier wave is 2,
,.

をω。とすれば、FM信号f (t)は、f (t) 
=ムsin (ωOt +m /V(t)dt+θ0)
(m、  θ0は定数) とあられされる。上記をディジタル信号の演算によって
実現した場合、標本化周期をT、変調信号の標本値をV
(nT)とすれば、FM信号f(nT)(n≧2) と書くことができる。
ω. Then, the FM signal f (t) is f (t)
=Mu sin (ωOt +m /V(t)dt+θ0)
(m, θ0 are constants) When the above is realized by calculating digital signals, the sampling period is T and the sample value of the modulation signal is V.
(nT), the FM signal can be written as f(nT) (n≧2).

ここでFM信号f(nT)の位相成分をθ(nT)とし
て、θ(nT )をNビットで量子化した場合を考える
。θ(nT)はNビットの量子化によって、0から2π
までを2)11固に分割され、量子化ステラがってθ(
nT)の計算をNビットを越える精度で行ってもNビッ
トを越える下位ビットは切り捨てられてしまうために、
位相振幅変換器の位相入力の語長をNビットとした場合
には、θ(nT)の計算を行う積分器の語長もNビット
あれば十分てあ3へ−・ る。つまり従来の構成では、積分器語長と位相振幅変換
器の位相入力語長を等しくしていた。
Here, let us consider a case where the phase component of the FM signal f(nT) is θ(nT), and θ(nT) is quantized with N bits. θ(nT) varies from 0 to 2π by N-bit quantization.
Up to 2) is divided into 11 parts, and the quantized Stella becomes θ(
nT) with a precision exceeding N bits, the lower bits exceeding N bits are discarded, so
If the word length of the phase input of the phase-amplitude converter is N bits, it is sufficient if the word length of the integrator for calculating θ(nT) is also N bits. In other words, in the conventional configuration, the integrator word length and the phase input word length of the phase/amplitude converter are made equal.

発明が解決しようとする問題点 しかしながら、上記の構成法では以下に示すような問題
点を有している。
Problems to be Solved by the Invention However, the above configuration method has the following problems.

適当な語長であられされた変調信号をNビットの階調で
変調しようとする場合には、積分器及び位相振幅変換器
の位相入力ともNビットの語長が必要である。ここで位
相振幅変換器はROM等を用いて構成する場合が多いが
、その場合その回路規模はNではなく 2Nに比例して
犬きくなる。したがって、Nが大きい場合例えば8ビツ
トや10ビツトの場合に、積分器に比べて位相振幅変換
器の回路規模は非常に大きくなり、階調をさらに」二げ
ようとしても問題が多い。
When attempting to modulate a modulated signal with an appropriate word length with N-bit gradations, the phase inputs of the integrator and phase/amplitude converter both require a word length of N bits. Here, the phase/amplitude converter is often constructed using a ROM or the like, but in that case, the circuit scale becomes larger in proportion to 2N rather than N. Therefore, when N is large, for example 8 bits or 10 bits, the circuit scale of the phase/amplitude converter becomes much larger than that of the integrator, and there are many problems even when attempting to further increase the gradation level.

問題点を解決するための手段 上記問題点を解決するため本発明は標本化周期Tで標本
化されたディジタル変調信号に、定数Cを加算する第1
の加3つ器と、内部に第2の加算器と遅延器とを有し前
記第1の加勢器の出力を入力として積分を行う積分器と
、前記積分器出力を人力として、正弦値あるいは余弦値
を出力する位相振幅変換器とを備え、前記積分器の語長
を前記位相振幅変換器の位相角の入力語長よりも、下位
方向に少なくとも1ビット以上長くしたものである。
Means for Solving the Problems In order to solve the above problems, the present invention provides a first method of adding a constant C to a digital modulation signal sampled at a sampling period T.
an integrator that has a second adder and a delay device inside and performs integration using the output of the first adder as input; and a sine value or and a phase/amplitude converter that outputs a cosine value, and the word length of the integrator is made longer by at least one bit in the lower direction than the input word length of the phase angle of the phase/amplitude converter.

作用 本発明は前記した構成により、適当なピッi・数であら
れされた入力変調信号をNビットの階調でFM変復調す
る場合に、変調信号以外の不用な周波数成分が発生し変
調を受けるが、変調信号の周波数が低いと上記の不用な
周波数の信号の振幅が小さく、かつ復調側の低域p波器
によって特定の周波数成分は減衰されるために、復調側
においてNビットの階調が得られる。
Effect of the Invention With the above-described configuration, the present invention eliminates the possibility that when an input modulation signal with an appropriate number of pitches is FM modulated and demodulated with N-bit gradation, unnecessary frequency components other than the modulation signal are generated and subjected to modulation. , when the frequency of the modulation signal is low, the amplitude of the above-mentioned unnecessary frequency signal is small, and the specific frequency component is attenuated by the low-frequency p-wave generator on the demodulation side, so the N-bit gradation is can get.

実施例 以下に本発明の実施例を添付図面を用いて説明する。Example Embodiments of the present invention will be described below with reference to the accompanying drawings.

第1図は、FM変調装置に本発明を実施した一例であっ
て、第1図において1は入力端子、2゜3は加算器、4
は遅延器、6は加算器3と遅延器6ペー/゛ 4から構成される積分器、6は位相角θを入力としてs
inθを出力する位相振幅変換器、7はD/A変換器で
ある。第2図は、FM復調装置であって、第2図におい
て8は入力端子、9はA/D変換器、1oはsinθを
入力としてsin (θ+9o)を出力する9C3移相
器、11は振幅位相変換器、12゜13は減算器、14
は遅延器、16は低域p波器、16はD/A変換器であ
る。
FIG. 1 shows an example in which the present invention is implemented in an FM modulation device, in which 1 is an input terminal, 2.3 is an adder, and 4 is an input terminal.
is a delay device, 6 is an integrator consisting of an adder 3 and a delay device 6/4, and 6 is an integrator with the phase angle θ as input.
A phase amplitude converter outputs inθ, and 7 is a D/A converter. FIG. 2 shows an FM demodulator, in which 8 is an input terminal, 9 is an A/D converter, 1o is a 9C3 phase shifter that receives sin θ as input and outputs sin (θ+9o), and 11 is an amplitude Phase converter, 12° 13 is a subtracter, 14
16 is a delay device, 16 is a low-frequency p-wave device, and 16 is a D/A converter.

(周波数変調) 端子1に入力されたディジタル変調信号は、加算器2で
定数C(搬送角周波数ωCと標本化周期での積)を加算
され、加算結果は加算器3と遅延器4から構成された積
分器6に入力される。積分器5で位相角θが計算され、
積分器6の出力は振幅位相変換器6に入力される。ここ
で積分器6の語長をNビットとし、位相振幅変換器6の
語長は、積分器6の最下位ビットを1ビット減らしたN
 −1ビツトとする。この場合に、入力変調信号の周波
数が低ければ、積分器5の出力の最下位ビットの変化が
標本化周期の2倍の周期で位相振幅変換6ベーツ・ 器6の位相角入力の最下位ビットにあられれる。
(Frequency modulation) The digital modulation signal input to terminal 1 is added with a constant C (product of carrier angular frequency ωC and sampling period) in adder 2, and the addition result is composed of adder 3 and delay device 4. is input to the integrator 6. The phase angle θ is calculated by the integrator 5,
The output of the integrator 6 is input to an amplitude phase converter 6. Here, the word length of the integrator 6 is N bits, and the word length of the phase/amplitude converter 6 is N bits, which is obtained by reducing the least significant bit of the integrator 6 by 1 bit.
-1 bit. In this case, if the frequency of the input modulation signal is low, the change in the least significant bit of the output of the integrator 5 is twice the sampling period as the least significant bit of the phase angle input of the phase amplitude converter 6 Bates 6. Hail to you.

したがって、変調信号V(nT)に標本化周波数の2分
の1の周波数の信号N(nT)が重畳された形で変調が
行われることになり、位相振幅変換器6の出力信号f 
(nT )は次のように表わされる。
Therefore, modulation is performed in such a way that the signal N(nT) having a frequency of one half of the sampling frequency is superimposed on the modulation signal V(nT), and the output signal f of the phase amplitude converter 6 is
(nT) is expressed as follows.

」二記一連の演算で得られたFM信号出力は、D/A変
換器7でアナログ信号に変換されるが、その際標本化周
波数の半分を越える周波数の信号は帯域内に折り返され
る。本実施例の場合には上からの折り返しと下からの折
り返しの周波数が一致し、FM信号周波数をfa、標本
化周波数をf8とすれば、折り返しの周波数f、は B f+  =   f。
The FM signal output obtained from the series of operations described in section 2 is converted into an analog signal by the D/A converter 7, but at this time, signals with a frequency exceeding half of the sampling frequency are folded back within the band. In the case of this embodiment, the frequencies of the folding from above and the folding from the bottom match, and if the FM signal frequency is fa and the sampling frequency is f8, the folding frequency f is B f+ = f.

で与えられる。is given by

(周波数復調) アナログFM信号は適当な伝送系を径だ後、以下の方法
で復調される。端子8から入力されたア7ベー、・ ナログ信号はA/D変換器9でディジタル信号に変換さ
れ、9d移相器1oに入力される。9♂移相器10から
は入力信号の位相を9♂シフトした信号が出力され、入
力信号と90″移相器出力信号の2つの信号の符号、振
幅及び振幅の大小関係から、振幅位相変換器11で位相
情報が出力される。
(Frequency demodulation) The analog FM signal is demodulated by the following method after passing through an appropriate transmission system. The analog signal inputted from the terminal 8 is converted into a digital signal by the A/D converter 9 and inputted to the 9d phase shifter 1o. The 9♂ phase shifter 10 outputs a signal in which the phase of the input signal is shifted by 9♂, and amplitude phase conversion is performed based on the sign, amplitude, and magnitude relationship between the two signals, the input signal and the 90'' phase shifter output signal. The phase information is outputted by the device 11.

減算器12で、上記振幅位相変換器11の出力と遅延器
14の出力との差分をとり、減算結果からさらに減算器
13で搬送周波数成分を除くことにより、変調信号が復
調される。捷た、振幅位相変換器11の出力は1標本化
周期後の演算のために、遅延器14に記憶される。ここ
で上記の折り返しの周波数成分も同時に復調され、変調
信号の上に周波数 f2−111−fol の成分が重畳された形であられれる。f2は変調信号の
周波数が低い場合には、搬送周波数fa によって変化
するが、この不用な周波数成分は振幅が小さくかつ低域
r波器15によって特定の周波数成分は減衰されるため
に、D / A変換器16の語長をNビット以上に選べ
ば、復調信号の中からNピット階調の変調信号がアナロ
グ信号に変換される。
A subtracter 12 takes the difference between the output of the amplitude phase converter 11 and the output of the delay device 14, and a subtracter 13 removes the carrier frequency component from the subtraction result, thereby demodulating the modulated signal. The output of the amplitude-phase converter 11 is stored in the delay unit 14 for calculation after one sampling period. Here, the folded frequency component described above is also demodulated at the same time, and the frequency component of frequency f2-111-fol is superimposed on the modulated signal. When the frequency of the modulation signal is low, f2 changes depending on the carrier frequency fa, but since this unnecessary frequency component has a small amplitude and a specific frequency component is attenuated by the low-frequency r wave generator 15, D/ If the word length of the A converter 16 is selected to be N bits or more, a modulated signal of N pit gradations from the demodulated signal is converted into an analog signal.

以上のように本実施例によれば、比較的低い周波数のデ
ィジタル変調信号をNビットの階調でFM変復調するに
あたり、FM変調における位相振幅変換器の位相角入力
語長を積分器語長よりも1ビット減らしたN−1ビツト
としても、復調側でNビットの階調を得ることができる
As described above, according to this embodiment, when FM modulating and demodulating a relatively low frequency digital modulation signal with N-bit gradation, the phase angle input word length of the phase amplitude converter in FM modulation is determined from the integrator word length. Even if the number of bits is reduced by one bit to N-1 bits, N-bit gradation can be obtained on the demodulation side.

なお、位相振幅変換器6では正弦値を出力するが、正弦
関数が周期関数であることから、一周期分の位相角に対
する正弦値をROMに記憶して、必要な時に読み出すよ
うにすればよい。また振幅位相変換器11では、FM信
号とFM信号を90’シフトした信号とから正弦値を求
め、4分の1周期分の正接値に対する位相角をROMに
記憶し読み出したものと、上記2つの信号の符号及び振
幅の大小関係から一周期分の位相角の値を求めれば良い
Note that the phase amplitude converter 6 outputs a sine value, but since the sine function is a periodic function, the sine value for one period of the phase angle may be stored in the ROM and read out when necessary. . In addition, the amplitude phase converter 11 calculates the sine value from the FM signal and the signal obtained by shifting the FM signal by 90', stores the phase angle for the tangent value for one-quarter period in the ROM, reads out the sine value, and calculates the sine value from the FM signal and the signal obtained by shifting the FM signal by 90'. The value of the phase angle for one cycle can be found from the magnitude relationship between the signs and amplitudes of the two signals.

次に、本発明を用いて実際にFM変復調を行っ、 9ペ
ージ た例を以下に示す。ここで入力変調信号を直流とし、搬
送周波数を適当な語長で表わせば、正弦値発生装置の入
力信号の階調は搬送周波数の語長で決定できる。したが
って搬送周波数の語長をNビットとし、積分器5の語長
をNビット、位相振幅変換器6の位相角入力語長をN−
1ビツトとしてFM変復調を行い、復調信号の階調を評
価した。
Next, an example of 9 pages of actual FM modulation and demodulation using the present invention is shown below. Here, if the input modulation signal is a direct current and the carrier frequency is expressed by an appropriate word length, the gradation of the input signal to the sine value generator can be determined by the word length of the carrier frequency. Therefore, the word length of the carrier frequency is N bits, the word length of the integrator 5 is N bits, and the phase angle input word length of the phase amplitude converter 6 is N−.
FM modulation and demodulation was performed as 1 bit, and the gradation of the demodulated signal was evaluated.

ただし上記正弦値発生装置とは第1図における加算器3
.遅延器4から構成された積分器6と位相振幅変換器6
を含めた装置のことを指すものとする。
However, the above sine value generator is the adder 3 in FIG.
.. An integrator 6 and a phase/amplitude converter 6 composed of a delay device 4
This refers to equipment including.

第3図は、復調後にp波器を通した波形であり、直流信
号(変調信号)に上記の変調器の構成によって生じた周
波数成分が重畳された形になっている。第4図、第5図
は、変調信号の周波数を変えた場合の不用な周波数成分
の振幅つまり第3図におけるaの大きさを示した図であ
り、第4図はH=5、第6図はl=9の場合である。両
図において横軸は周波数で、1周期(0〜2π)をN−
1ビツトで量子化しており、縦軸は不用な周波数酸1o
ベーI′ 分の振幅で、flN−+がN−1ビツトの分解能、1l
)IがNビットの分解能である。第4図、第5図ともに
、変調信号に重畳された不用な周波数成分の振幅はNビ
ットの分解能よりも小さくなっている。
FIG. 3 shows a waveform passed through a p-wave modulator after demodulation, in which a frequency component generated by the above modulator configuration is superimposed on a DC signal (modulation signal). 4 and 5 are diagrams showing the amplitude of unnecessary frequency components when the frequency of the modulation signal is changed, that is, the size of a in FIG. 3. The figure shows the case where l=9. In both figures, the horizontal axis is the frequency, and one period (0 to 2π) is expressed as N-
It is quantized by 1 bit, and the vertical axis is the unnecessary frequency acid 1o.
With amplitude equal to be I', flN-+ has a resolution of N-1 bits, 1l
) I is the resolution of N bits. In both FIG. 4 and FIG. 5, the amplitude of the unnecessary frequency component superimposed on the modulated signal is smaller than the resolution of N bits.

つまり、Nビットの信号を正弦値発生装置に入力した場
合に、位相振幅変換器の位相入力語長がN−1ビツトで
あっても復調側においてNビットの階調が得られること
が確認できる。
In other words, it can be confirmed that when an N-bit signal is input to the sine value generator, an N-bit gradation can be obtained on the demodulation side even if the phase input word length of the phase-amplitude converter is N-1 bits. .

なお、第4図、第5図ともに周波数によって振幅が違っ
ており、特に第4図においては低い周波数でNビットの
階調が得られていないが、これは上記実験で使用した9
0移相器及び低域p波器の周波数特性が原因していると
考えられる。9d移相器ならびに低域p波器の伝達関数
は以下の通りである。
Note that in both Figures 4 and 5, the amplitude differs depending on the frequency, and in Figure 4 in particular, N-bit gradation is not obtained at low frequencies, but this is due to the 9 bits used in the experiment above.
It is thought that this is caused by the frequency characteristics of the 0 phase shifter and the low-pass p-wave shifter. The transfer functions of the 9d phase shifter and the low-pass p-wave shifter are as follows.

9o移相器 H(z)=(1/12g)(3(1−Z  )+a(Z
2−z”)+21(z’−Z”)+79(Z ’低域p
波器 117  。
9o phase shifter H(z)=(1/12g)(3(1-Z)+a(Z
2-z") + 21 (z'-Z") + 79 (Z' low range p
Wave device 117.

H(z)=(1/266)(−2(1−Z  )+7(
Z−Z  )−20(Z  −Z  )−1−79(Z
  −Z   )+128Z  ) 発明の詳細 な説明したように、本発明による周波数変調装置を用す
ることによって、位相振幅変換器の入力を従来よりも少
ない語長で構成できるため、位相振幅変換器の回路規模
が大幅に小さくなる。また位相振幅変換器は従来のま1
でも、変調信号の周波数が低い場合には、積分器の語長
を増やすだけで階調をあげることができる。つまり細か
い変化の部分に対しては効果がないが、比較的平らな部
分に対しては、積分器の語長を下位方向に1ビツトある
いはそれ以」二増やすという簡rliな回路の付加によ
って階調をあげることができる。−また、位相振幅変換
器の入力語長を少なくできれば、それ以後の例えば位相
振幅変換器の出力、D/A変換器などの語長も少なくで
きることが期待される。
H(z)=(1/266)(-2(1-Z)+7(
Z-Z)-20(Z-Z)-1-79(Z
-Z)+128Z) As described in detail, by using the frequency modulation device according to the present invention, the input of the phase-to-amplitude converter can be configured with a word length smaller than that of the conventional one, so that the circuit of the phase-to-amplitude converter can be The scale will be significantly smaller. In addition, the phase-amplitude converter is the same as the conventional one.
However, if the frequency of the modulation signal is low, the gradation can be increased simply by increasing the word length of the integrator. In other words, it is not effective for parts with small changes, but for relatively flat parts, adding a simple circuit that increases the word length of the integrator by 1 or more bits in the lower direction can increase the level of change. You can raise the tone. - Furthermore, if the input word length of the phase-amplitude converter can be reduced, it is expected that the word length of subsequent outputs of the phase-amplitude converter, D/A converter, etc., can also be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による周波数変調装置の一実施例のブI
J ツク図、第2図は周波数復調装置のブロック図、第
3図は本発明を用いて実際に変復調を行った場合の復調
波形図、第4図、第6図は、変調信号の周波数を変えた
場合の復調波形における不用な周波数成分の振幅をあら
れした波形図である。 3・・・・・・加算器、4・・・・・・遅延器、5・・
・・・・積分器、6・・・・・・位相振幅変換器。
FIG. 1 shows a diagram of an embodiment of a frequency modulation device according to the present invention.
Figure 2 is a block diagram of the frequency demodulator, Figure 3 is a demodulated waveform diagram when modulation and demodulation is actually performed using the present invention, and Figures 4 and 6 are diagrams showing the frequency of the modulated signal. FIG. 4 is a waveform diagram showing the amplitude of unnecessary frequency components in the demodulated waveform when the amplitude is changed. 3...Adder, 4...Delay unit, 5...
...Integrator, 6...Phase amplitude converter.

Claims (1)

【特許請求の範囲】[Claims] 標本化周期Tで標本化されたディジタル変調信号に、定
数Cを加算する第1の加算器と、内部に第2の加算器と
遅延器とを有し前記第1の加算器の出力を入力として積
分を行う積分器と、前記積分器出力を入力として、正弦
値あるいは余弦値を出力する位相振幅変換器とを備え、
前記積分器の語長を前記位相振幅変換器の位相角の入力
語長よりも、下位方向に少なくとも1ビット長くしたこ
とを特徴とする周波数変調装置。
A first adder that adds a constant C to a digital modulation signal sampled at a sampling period T, and a second adder and a delay device inside, and inputs the output of the first adder. an integrator that performs integration, and a phase-amplitude converter that receives the integrator output as input and outputs a sine value or a cosine value,
A frequency modulation device characterized in that the word length of the integrator is made longer by at least 1 bit in the lower direction than the input word length of the phase angle of the phase amplitude converter.
JP60283537A 1985-12-17 1985-12-17 frequency modulator Pending JPS62142402A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60283537A JPS62142402A (en) 1985-12-17 1985-12-17 frequency modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60283537A JPS62142402A (en) 1985-12-17 1985-12-17 frequency modulator

Publications (1)

Publication Number Publication Date
JPS62142402A true JPS62142402A (en) 1987-06-25

Family

ID=17666815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60283537A Pending JPS62142402A (en) 1985-12-17 1985-12-17 frequency modulator

Country Status (1)

Country Link
JP (1) JPS62142402A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682431A (en) * 1993-12-07 1997-10-28 Hitachi Denshi Kabushiki Kaisha FM stereo broadcasting apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682431A (en) * 1993-12-07 1997-10-28 Hitachi Denshi Kabushiki Kaisha FM stereo broadcasting apparatus and method

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