JPS62143143A - Branch trace control system - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware by checking whether a branching source address and a branched address are included within previously set upper and lower limit addresses by an existing arithmetic circuit. CONSTITUTION:The upper and lower limit addressed of the branching source address and the branched address are stored in an LS area 51 of a main storage in addition to a pointer and a byte counter. When a branching condition is formed and branching is executed, the branching source address and the branched address are set up on one input of the arithmetic circuit (ALU) 1 and the upper and lower limit addresses stored in the specific area are extracted and set up to the other input to execute four operations. A carry/output zero detecting circuit 9 inputs a carry output to be '1' when the calculated result of the ALU 1 is a negative value and a zero output to be '1' when the calculated result is zero to test the input.

Description

[Detailed Description of the Invention] [Summary] In the branch trace control 11 mainly used for the purpose of dehasogging and diagnosis, it is determined whether a branch source address and a branch destination address are within a preset upper limit address and lower limit address range. This check is performed using an existing arithmetic circuit, thereby reducing the amount of hardware required.

[Industrial Field of Application] The present invention is mainly used for dehasogging and diagnostic purposes, and is directed to a control method for branch tracing in which the instruction addresses of the branch source and branch destination are stored in the main memory when a branch condition is met. Regarding.

[Prior Art] In branch trace control, specific address ranges are often set for branch source and branch destination addresses.
It is necessary to compare the branch source and branch destination addresses when branching by a branch instruction with the upper and lower limit addresses of the set address range.

In the prior art, it was necessary to provide a dedicated comparison circuit to compare the branch source and branch destination addresses with the upper and lower limit addresses.

FIG. 5 is a block diagram of a conventional method of branch trace control.

In FIG. 5, l is an arithmetic and logic unit (ALU), 2 is an A register (AR), and 3 is a B register (BR).
), 4 is an instruction address register (iAR), and 6 is a Z register (ZR), each of which is one of the main components of the central processing unit.

51 and 52 indicate partial areas of the main memory (MS) 5, 51 is an area called local storage (LS), and 52 is a table (hereinafter abbreviated as BT child table) in which addresses of branch destination and branch source are written. This is the area in which to write.

81, 82.83. and 84 are registers and comparison circuits provided for branch tracing.

81 is a register (L-LMT) for setting the lower limit address.
-REG), and 82 is a register (U-LMT-REG) for setting the upper limit address.

83 is a comparison circuit 1, which is an instruction address register (iA
The contents of R) 4 and the contents of L-LMT-REG 81 are compared, and 84 is a comparison circuit 2, which compares the contents of instruction address register (iAR) 4 and the contents of U-LMT-REG 82.

When performing a branch trace, first the main memory LS
A pointer indicating the start address on the BT child table 2 where the branch destination address and branch source address are to be stored and a byte count indicating the remaining area of the BT child table are written in the area 51, and the lower limit of the branch source and branch destination address is written. Set the address to L-LMT-RIEG 81 and the upper limit address to U-LMT-REG 82.

The contents of the instruction address register iAR are checked by a comparator circuit 1 to see if they are greater than or equal to the lower limit address, and by a comparator circuit 2 to see if they are less than or equal to the upper limit address, and if both are true, an AND gate 85 is opened. , BT OK (+BT-OK) becomes 1''.

The BT enable (+BT-ENB) signal is a signal that the operator can arbitrarily send, and when it is desired to branch,
Set it to 1".

If BT enable is set to "1" and BT OK is "1", AND gate 7 is opened and LS5
The branch source and branch destination addresses are written to the BT table address indicated by the pointer in 1, the pointer is added by the number of bytes of write data, the byte count is subtracted by the number of bytes, and the next start address and the number of remaining bytes are written. will be updated to show.

In this way, in the conventional method, dedicated registers L-LMT-REG and U-LMT-R are used for branch tracing.
EG1 and comparator circuit 1.2 are required.

[Problems to be Solved by the Invention] As described above, the conventional method requires a dedicated register and comparison circuit for branch tracing.

The present invention aims to provide a novel branch trace control method that does not require such dedicated registers and comparison circuits and reduces the amount of hardware.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the branch trace control method of the present invention.

In FIG. 1, the same reference numerals as in FIG. 5 indicate the same objects.

When performing a branch trace, first set the L of ta above.
In the S area 51, in addition to the pointer and hide count,
Store the upper and lower limit addresses of the branch source and branch destination addresses. This is performed by an auxiliary processor, such as a so-called service processor.

When the branch condition is satisfied and the branch is executed, the arithmetic circuit (AL
U) Set the branch source address and then the branch destination address to one input of l, retrieve and set the upper limit address and lower limit address stored in the specific area to the other input for each of them, and address) - (branch source address), ■ (upper limit address) - (branch source address), ■
The following four operations are executed: (lower limit address) - (branch destination address), (2) (upper limit address) - (branch destination address).

9 is a carry and output zero check circuit, which is an arithmetic circuit (
The following test is performed by inputting a carry output, which becomes "1" when the operation result of ALU)1 is negative, and a zero output, which becomes "1" when the operation result is zero.

That is, the carry output is "51" or the zero output is "1" as a result of the operations of ■ and ■, and the carry output is "O" or zero as the result of the operations of ■ and ■. When all the conditions for the output to be "1" are satisfied, the BT OK signal is set to "1".

If BT enable is set to l1t11 and BT OK becomes "1", AND gate 7 is opened and L
The branch source and branch destination addresses are written to the BT table address indicated by the pointer in S51, the pointer is added by the number of bytes of write data, the byte count is subtracted by the number of bytes, and the next start address and the number of remaining bytes are written. This is the same as in the conventional example.

[Operation] It will be explained below that the above configuration allows checking whether the branch source and branch destination addresses are within the set upper and lower limit addresses.

Branch source (same as branch destination) address (set to X)
are the lower and upper limit addresses (L-LMT, U-LM
T), there are the following five cases as shown in FIG. 2 (al).

■X < l-LMT.

■x = L-LMT.

■L-LMT< x < II-L old\■x=U-L
Elbow, ■ Ll-LMT< x.

The carry output and zero output for the operation results of (L-LMT)-x and (11-LMT)-x for each of the above five cases are as shown in FIG. 2 (bl).

Therefore, (L-LMT) -x and (U-LMT) -x when the branch source or branch destination address X is within the upper and lower limit addresses, that is, at ■, ■, ■.
The common OK conditions for carry output and zero output for the operation results are as shown in the bottom column of FIG. 2(b), and if these are satisfied by the four operations, BT is OK.

By performing the comparison operation using the existing arithmetic circuit as described above, there is no need for a dedicated register of about 4 bytes and a comparison circuit as shown in 81 to 84 in the conventional example.
This requires only an extremely small 1-bit circuit as shown in 9, and the amount of hardware can be greatly reduced.

EXAMPLES] The present invention will be described in more detail below with reference to examples shown in FIGS. 3 and 4.

FIG. 3 is a block diagram of an embodiment of the invention.

FIG. 4 is a time chart of an embodiment of the present invention.

In FIG. 3, the same reference numerals as in FIG. 4 indicate the same objects.

Reference numerals 91 to 95 designate example circuits of the contents of the carry and zero output test circuit 9 shown in FIG.

91 is an exclusive OR circuit (EOR), which is an arithmetic circuit (
The carry output of ALU) 1 and the output of cycle current 92 are input.

The cycle counter 91 is a circuit that counts -1 by a clock and resets it to "0" by its own output. Therefore, as shown in the time chart of Fig. 4, "0" and "1" are counted every cycle. repeat.

Reference numeral 93 denotes an OR gate, which receives the output of the EOR 91 and the zero output of the arithmetic unit (ALU) 1 as inputs.

94 is an AND gate, which receives the output of the OR gate 93 and the output of the circuit 95 as inputs.

The circuit 95 is a circuit that is reset to "1" by the output of the OR gate 93 and becomes "0" in the next cycle.

In the first cycle ■, if the cycle count 92 is "0" and the carry output is "l", then EOR92
The output of is "1".

When the output of EOR92 becomes "1", the output of OR gate 93 becomes "1" regardless of the value of zero output, and circuit 95
is "1" in the initial state, the output of the AND gate 94 becomes "l", and the circuit 95 is reset to "l".

In the next cycle (2), the cycle runt 92 becomes "1", and if the carry output is "0", the output of the EOR 91 becomes "1".

Therefore, the output of the AND gate 94 becomes "1" and the circuit 95 is reset to "1".

In the next cycle ■, the cycle count 92 is “0” again.
Then, the same thing as in cycle (■) is performed.

In the next cycle ■, cycle count 92 is “1” again
Then, the same thing as in cycle (2) is performed, and the AND gate 94 outputs BT-OK "1".

In each cycle above, if the zero output becomes "1", EO
Even if the output of R91 is 0, the output of AND gate 94 is 1.

If there is even one cycle in which the output of the OR gate 93 is "0" among the four cycles of ■, ■, ■, ■ above,
The output of the AND gate 94 becomes "0", and the circuit 95 becomes "0".
1” and the output of the AND gate 94 is “O”.
”.

When the branch condition is satisfied and a branch is taken in the circuit of FIG. 3, the situation in which branch tracing is executed is as follows, as shown in the time chart of FIG. 4.

(1) L-LMT is sent from LS to the A register (AR), and a branch source address is set to the B register (BR). The cycle count at this time is "0".

(2) In the next cycle, the AR-BR calculation is performed in the ALU, and the carry and cello output of the calculation result is checked by circuits 91 to 95.

(3) U-LMT is sent to the AR from the LS. The cycle count will be 1''.

(4) In the next cycle, the AR-BR calculation is performed in the ALU, and the carry and cello output of the calculation result is checked by circuits 91 to 95.

(5) The branch destination address is set from the instruction address register (iAR) in BR, and the LL revision from LS is set in AR. The cycle count becomes "0".

(6) In the next cycle, the AR-BR operation is performed in the ALU, and the carry and zero output of the operation result is checked in the circuits 91 to 95.

(7) U-LMT is set in AR from LS. The cycle count will be 1”.

(8) In the next cycle, the AR-BR operation is performed in the ALU, and the carry and zero output of the operation result is checked in the circuits 91 to 95.

(9) If the output of the A'ND gate 94, ie, BT-OK, is "1", the branch source address in the Z register (ZR) and the branch destination address in BR are written into the BT child table.

(10) The hide count from LS force 1 is set in A R, and 8" is set in BR. The value of "8" is B
This is because the branch source and branch destination address data written in the T child table is 8 hides.

(11) In the next cycle, at A + - U, A R
An operation of -+3R is performed and the value of hide count in LS is updated by the result.

(12) A pointer is set in AR from LS.

(13) In the next cycle, in ALU, AR+BR
is performed, and the value of the pointer in LS is updated according to the result.

This completes one branch trace, and preparations for the next branch trace are complete.

[Effects of the Invention] As explained above, according to the present invention, since address comparison is performed using existing arithmetic circuits, hardware stars can be reduced, and the practical effects thereof are extremely large. .

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a diagram showing BT okay conditions, Fig. 3 is a block diagram of an embodiment of the present invention, Fig. 4 is a time chart of an embodiment of the present invention, and Fig. 5 is a diagram showing the BT OK condition. The figure is a block diagram of a conventional example. In the drawing, 1 is an arithmetic circuit (ALU), 2 is an address register (AR), 3 is a B register (BR), 4 is an instruction address register (iAR), 5 is a main memory,
6 is the Z register (ZR), 7 is the AND gate, 9 is the carry and zero output check circuit, 51 is the LS area, 52 is the BT child table area, 8
1, 82 are registers, 83.84 are comparison circuits, 85
is an AND gate, 91 is an exclusive OR circuit (EOR), 92 is a cycle count, 93 is an OR gate, 94 is an A
ND gate, 95 indicates a reset circuit, and 95 indicates a reset circuit. Principle block diagram of the present invention Fig. 1(b)

Claims (1)

[Claims] In a data processing device equipped with a branch trace function that stores instruction addresses of a branch source and a branch destination in a specific area of a main storage device when a branch condition is satisfied, means for setting upper and lower limit addresses in specific areas of main memory; On the other hand, control means takes out and sets the upper limit address and lower limit address stored in the specific area to the other input, and executes four calculations; the carry output and the zero output of the calculation circuit are input; a carry and zero output inspection circuit that inspects the carry output and zero output in the results of each operation, and outputs a signal permitting branch tracing when all the operation results of each operation satisfy a predetermined condition; A branch trace control method, comprising: a computation operation for comparing the branch source and branch destination addresses with the upper limit value and the lower limit value using an arithmetic circuit included in the data processing device.