JPS62143151A - Diagnosis system for common memory - Google Patents

Abstract

PURPOSE:To improve diagnosis accuracy by forming an area for storing instructions, responses and detailed information obtained from a processor at the time of diagnosis in a common memory and connecting an information means for informing an interruption signal between processors. CONSTITUTION:At the normal transmission of a START instruction, a microprocessor (muP) 2 checks the writing/reading of the specified address and a muP 3 also checks writing/reading independently of the muP2. The muP3 specifies an address to the muP2 so that the address to be checked by itself is not overlapped by the address checked by the muP2 and the muP2 and muP3 check a local memory (LM) 5 respectively independently. Since accessed from the muP2, muP3 to the LM 5 may be sometimes competed, diagnosis including an arbiter 6 can be attained. When the diagnosis of the specified address is normally ended, a response 1 is written in a response field to interrupt the muP3 and the muP3 receives the response 1 to confirm the normal end of the diagnosis. Consequently, the diagnosis of a memory competition circuit can be efficiently executed.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a shared memory diagnostic method.

(Prior Art) FIG. 2 is a schematic configuration diagram of a communication control device having a shared memory. In Fig. 2, 1 is an interface unit (I/1'') that interfaces with a host device (not shown), 2 is a microprocessor (slave), 3 is a microprocessor (master), and l is a lower part (not shown). Interface unit (1/F) that interfaces with the device, 5 is μP2
, μP3, and is called a local memory IJ (LM). 6 is LM
7 is an address line, 8 is a data line, 9 is an interrupt line, 10 is an address line, and 1 is a data line.

How the LM 6 was conventionally diagnosed with such a configuration will be explained below.

Figure 3 shows the flow of this diagnosis. In the first step, μP3 writes specific data to a predetermined area of LM 5 (W), and then reads this data from LM 5 (R). These data are compared and checked, the address is updated, and the same process is repeated to diagnose a predetermined area of the LM 5. After that, μP3 notifies μP2 of the end of diagnosis via interrupt line 9 (IPT). In the second stage, μP2 similarly diagnoses a predetermined area of LM 5 in response to this interrupt. After that, μP2 notifies μP3 of the end of diagnosis via interrupt line 9 (IPT). In the third step, μP3 diagnoses another area of LM 5 again. These steps are repeated 9 times below.

(Problems to be Solved by the Invention) As described above, in the conventional shared memory diagnosis, one microprocessor had to finish the diagnosis before the other microprocessor could diagnose the other microprocessor.

Therefore, there was a problem that diagnosis took a long time.

In addition, it is not possible to check shared memory access when a so-called conflict occurs, where both microprocessors access the shared memory at the same time.
There was a problem that the arbiter could not be checked.

It is an object of the present invention to eliminate the above-mentioned problems that diagnosis takes time and problems that competitive circuit parts cannot be checked, and to improve diagnostic accuracy.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a diagnostic method for a shared memory shared by a plurality of processors. An area for storing detailed information is provided, and notification means using interrupt signals is provided between the processors. When diagnosing, the master processor writes address information to the detailed information storage area, and in response, this address information is sent to other processors. The processor reads it, and other processors check the write/read of a predetermined address in the shared memory based on this address information.The master processor checks the write/read of a predetermined address in parallel, and the other processors complete the above check. Then, the check result is written in the response information storage area, and upon receipt of this, the master processor reads this response information storage area and learns the check results of other processors.

(Function) With the above configuration, the other processors diagnose the shared memory independently of the master processor based on the address information. Furthermore, since the master processor and other processors diagnose the shared memory in parallel, the arbiter section is also checked at the same time.

Therefore, the above problem can be eliminated.

(Example) FIG. 1 is a configuration diagram of a shared memory according to the present invention.
The memory contents of the LM 5 shown in the figure are shown. In Fig. 1, address A instructs the other processor to diagnose the content.
The command/response area (CMD/RES area) is where you can check the results, the area from address B is used by μP2 in Figure 2, and the area from address C is used by μP2 in Figure 2.
This area is shared and commonly used by P2 and μP3, and the area from address D is used by μP3 in FIG.

Here, the CMD/RES area is a fixed area for initial diagnosis of LMs, and other areas are determined by the system.

FIG. 4 is a detailed configuration diagram of the CMD/RES area in FIG. 1, where CMD is a command field for instructing diagnosis contents, RES is a response field for storing diagnosis results,
DETAILO; 1, . . . n are fields for storing detailed information.

Table 1 shows details of the C>ff)/RES field.

For example, command 1 is a command that instructs the address range to be rejected, and DETAIL O and l store the first address and the last address, respectively. Command 2 is an analysis start command for the already designated address range. Response 1 indicates that the diagnosis has ended normally, and response 2 indicates that the diagnosis has ended abnormally.D
ETAILO contains details of the abnormality), response 3 indicates that the address was received normally, and response 4 indicates that the diagnosis start command was received normally.

Next, the diagnostic operation of the shared memory will be explained using the sequence chart of FIG.

[■Processing]

An interrupt is generated from μP3 to μP2. When this interrupt is normally received, an interrupt is generated from μP2 to μP3.

By checking this interrupt, the check of the interrupt line 9 in FIG. 2 is completed.

[■Processing]

μP3 stores the specified data (
For example, "5555 (hexadecimal)") is written and an interrupt is issued to μP2 (indicated by symbol W in FIG. 5). μP2 reads the data in the CMD/RES area (indicated by the symbol R in Figure 5) and checks whether the data is '5555 (hexadecimal). (hexadecimal)″)
is written and interrupts μP3. μP3 is CMD
/ RES area data is read and the data is "AA"
AA (hexadecimal)''.This will cause C
Confirm that the information can be retrieved correctly using the MD/RES area.

[■Processing]

μP3 writes data indicating command 1 (address instruction) to the CMD field of LM5, and then writes DETA
Start address to be diagnosed in ILO field, DETAI
Write the final address in the LI field and issue an interrupt to μP2. After μP2 normally receives command I and takes in the address information, it writes response 3 (address normal reception) to the RES field and interrupts μP3. μP3 reads response 3 and confirms that the address information has been successfully passed to μP2.

[■Processing]

μP3 enters command 2 (S) in the CMD field of LM5.
TART instruction) is written and an interrupt is applied to μP2. μP2 successfully receives command 2 and R
Write response 4 (normal reception of START instruction) to the ES field and issue an interrupt to μP3.

μP3 reads response 4 and confirms that the 5TART instruction information has been successfully passed to μP2. This is υC
Diagnosis of areas other than the MD/RES area is started.

[■Processing]

When the 5TART instruction is transmitted normally, μP2 performs a write/read check on the specified address. μP
The area checked by μP2.2 in FIG. μ
This is an area of P2/μP, 3. Also, μP3 and μP2
Write/read checks are performed regardless of the

The area checked by μP3 is μP3 in Figure 1.
．． This is the area of μP27μP3. Note that μP3 instructs μP2 to address so that the address it checks and the address checked by μP2 do not overlap.

In this way, μP2 and μP3 independently check LM5.

At this time, since accesses to LM 5 from μP2 and μP3 may conflict with each other, diagnosis including the arbiter 6 in FIG. 2 can be performed. RE when the diagnosis of the indicated address is completed normally.
Writes response IC diagnosis (normal completion) in the S field and interrupts μP3.

μP3 receives response 1 and confirms that the diagnosis of μP2 has been completed normally. At this time, if there are still areas left for μP2 to check, the remaining areas are checked in the same manner. At this time, as described above, μP3 instructs μP2 to address so that the address it checks and the address checked by μP2 do not overlap.

Although the explanation in FIG. 5 is based on the assumption that a normal response is returned to μP3, in reality, no response may be returned, or an abnormal response may be returned.

Of course, μP3 has an abnormality processing function for this purpose.

As described above in detail, the present invention is not limited to a method for diagnosing a shared memory shared by two processors as shown in FIG. Also good. In this case too, CMD/
Diagnosis is performed in the same manner as above using the RES area.

Table 1 (Effects of the invention) As explained in detail above, according to the present invention, the opponent μP
Since the address information of the shared memory to be diagnosed is passed to the user, it is expected that the diagnosis can be completed in the minimum necessary time.

In addition, since the own μP can manage the addresses to be diagnosed by the other μP, by selecting the address, a shared memory rush test can be easily implemented without instructions from a higher level, and the memory contention circuit (arbiter) can be diagnosed. This has the effect of making it possible to do this more efficiently.

Additionally, since we have made it possible for the master μP to control shared memory allocation, we expect that it will be possible to easily respond to different allocations depending on the system by partially changing the address management of the master μP. can.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a shared memory according to the present invention, FIG. 2 is a schematic configuration diagram of a communication control device, FIG. 3 is a sequence chart diagram showing conventional shared memory diagnosis, and FIG. C
FIG. 5 is a detailed configuration diagram of the MD/RES area, and is a sequence chart showing the diagnostic operation of the shared memory. 2.3: Microprocessor, 5: Shared memory. Present invention 1 bMlt "To the island structure" Fig. 1 A device for chanting. 3 Figure IIn, ICMD/RESXJ7/3! Itokyu Maki Am Figure 4

Claims (1)

[Claims] In a diagnostic method for a shared memory shared by multiple processors, an area is provided in the shared memory to store instructions from the processor, responses from the processor, and detailed information during diagnosis, and furthermore, an area for storing instructions from the processor during diagnosis, responses from the processor, and detailed information is provided, and furthermore, an area is provided for storing instructions from the processor during diagnosis, and detailed information is stored between the processors. A signal notification means is provided, and when diagnosing, the master processor writes address information in the detailed information storage area, and other processors read this address information, and the other processors write the shared memory based on this address information. The master processor performs a write/read check on a predetermined address, and in parallel, the master processor also performs a write/read check on a predetermined address. When the other processors complete the above check, they write the check result into the response information storage area and receive it. A shared memory diagnostic method is characterized in that a master processor reads this response information storage area and learns the check results of other processors.