JPS62143473A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to an ultra-fine MO8 type transistor suitable for making a source/drain diffusion layer horizontal.

Furthermore, the present invention relates to a semiconductor device, and particularly to an ultrafine MO8 type field effect transistor (hereinafter simply abbreviated as a transistor) that can alleviate a strong drain electric field without reducing current gain and therefore has excellent hot carrier resistance.

[Background of the invention]

As semiconductor integrated circuit devices become more highly integrated, their constituent elements, MO8 field effect transistors (hereinafter simply abbreviated as MOS), are becoming smaller, and the junction depth of source and drain diffusion layers also tends to become horizontal. . A problem in constructing shallow junctions is the occurrence of failures in junction penetration due to the eutectic of aluminum (AQ) and silicon (Si), which are wiring materials. In the conventional MOS, as shown in FIG. Diffusion layers 20 and 21 are formed to prevent the AQ-8i eutectic from breaking through the junction.

In FIG. 2, 1 is a P conductivity type silicon substrate, 2 is a filled oxide film, 15 is an interlayer insulating film, and the n-source diffusion layer 71. The drain diffusion layer 81 is formed using the gate electrode 4 and the gate protection insulating film 5 as a mask. 3 is a gate insulating film.

The source and drain n+ diffusion layers 18 and 19 are formed using the gate sidewall insulating film 6 as a mask.

In the conventional structure shown in FIG. 2, the deep diffusion layers 2o and 21 that prevent the AQ-5i eutectic from penetrating the junction are usually formed after the interlayer insulating film 15 is deposited and holes are opened at desired locations. It is formed using the implantation method. Therefore, in order to activate the implanted ions, a high-temperature heat treatment process at around 1000°C is applied to the n- diffusion layers 71, 8]-, n+ diffusion layers 18,
and 19 after formation. Therefore n
- Diffusion layer 71. When attempting to make the bonding depths of the bonding depths of the bonding depths of the bonding layers 81, 18, and 19 into horizontal bars, it is impossible to make the bonding depths more than a certain value as long as the above-mentioned high-temperature heat treatment step is required. In Figure 2, the source/drain diffusion layers are phosphorous (P).

Alternatively, in the case of a so-called n-channel MOS made of an n-type impurity such as silicon (As), the source/drain diffusion layer is made of a p-type impurity such as boron (B), which has a fast diffusion rate. In the case of the so-called P-channel MO8, it is particularly difficult to create horizontal beams. n10 diffusion M20 with deep junction.
If the temperature of the heat treatment step for forming the electrodes and 21 is lowered, the activation of impurities will be reversed to some extent, but other defects such as junction leakage will occur, which is not preferable.

As another means to prevent junction penetration caused by AQ-8i products, tungsten (
Silicide such as W) or molybdenium (M o ) is formed, and after depositing an interlayer insulating film and opening holes at desired locations, the silicon substrate surface sprayed out through the holes is covered with a W film, and then A
The method for implementing the fl wiring process is also disclosed in Japanese Patent Application Laid-Open No. 59-20575.
9 etc.

In the above structure, the W film acts as a barrier to diffusion of Sl or A 2 O, and has the effect of preventing junction penetration.

The above structure in which the source/drain diffusion layer is silicided is extremely preferable as an ultra-fine MOS because the sheet resistance of the diffusion layer is sufficiently low even on the cross-shaped diffusion layer □. silicide structure of the source/drain diffusion layer;
Two hot springs -・', 1. The sheet resistance of the silicide film is about 6B to LOΩ/2, which is a high resistance for a silicide film, and the surface condition is extremely uneven, making it undesirable for application to further miniaturized MOS. Titanium (T i ) silicide film has a sheet resistance of about 2 Ω/hole, which is the lowest resistance among silicide films of high-melting point metals, and the surface condition is extremely flat, making it super 4iRMO5.
This is preferable for application to silicidation of source/drain diffusion layers. However, there are also serious problems in the application of the Ti silicide film. That is, when forming holes in the glabella insulating film to connect the electrode to the silicide film on the source/drain diffusion layer, the etching rate of the interlayer insulating layer and the Ti
Since there is no large difference in the etching rate of the silicide film (hereinafter referred to as TiSi film, but the composition ratio of Ti and Si is not limited to 1:2), the TiSi2 film in the opening is easily removed. It is. Therefore, n+ source・
In the case where the drain diffusion layer is extremely shallow (less than 50 mm), the n/diffusion layer is also removed at the same time, and an extreme case may occur in which the W film directly contacts the n- diffusion layer or the silicon substrate. In the above case, high resistance nonlinear characteristics or shot rectification characteristics are exhibited, making it impossible to obtain good low resistance ohmic characteristics.

The horizontal cross-section of the source train diffusion layer due to the miniaturization of transistors results in an increase in the resistance of the diffusion layer.

In order to prevent a decrease in current gain due to an increase in diffusion layer resistance, in ultrafine transistors, a high-intensity metal film or a metal silicide layer (hereinafter referred to as a silicide layer) is placed on the surface of the diffusion layer in self-alignment with the source/drain diffusion layer. The method of configuring is publicly known. Furthermore, in transistors with a channel length of 1 μm or less, the present inventors have also patented a drain diffusion layer structure that has a sufficiently high source-drain breakdown voltage to prevent hot carrier injection deterioration even during normal power supply operation of 5V. Showa 5
It has already been filed as No. 9-205759 and has a configuration as shown in FIG. In FIG. 8, 1 is a P conductivity type silicon substrate, 2 is a thick filled oxide film for isolation between elements, 3 is a gate oxide film, and 60 and 70 are a gate electrode 4 and a gate protection insulator 1! A first plate selectively formed on the side wall of A5.
This is the gate sidewall insulating film. Reference numerals 8o and 90 denote a source region and a drain region formed of low concentration (n-) diffusion layers, respectively, and are formed using the first gate sidewall insulating films 60 and 70 as a diffusion mask. n-source diffusion layer 80, and n-source diffusion layer 80;
- Silicide layers 12 and 1 on the surface of the drain diffusion layer 90
A source electrode 17 and a drain electrode 18 are connected to each other via a barrier metal layer 15 and a barrier metal layer 1G. 14 is an interlayer insulating film. In a known transistor as shown in FIG.
0 is the n-source diffusion layer 80 and the n-drain diffusion layer 90
It has a role as an introductory point. The role of the n-drain diffusion layer in ultrafine transistors is to alleviate the strong drain electric field, and its impurity concentration, junction depth,
Furthermore, there are optimum conditions for the distance between the silicide layer 13 and the gate electrode t4i4, etc. based on the desired circuit nitric acid. Among the above conditions, the optimal condition for the impurity concentration can be set independently of the gate sidewall insulating films 60 and 70, but the junction depth cannot be set independently of the distance between the silicide layer 13 and the gate electrode 4, that is, the thickness of the gate sidewall insulating film. In particular, when the spacing between the silicide layer 13 and the gate electrode is set to a desired value, conduction between the drain, solenoid and single layers is not guaranteed unless the junction depth is set to be greater than the set value. Conventionally, the gate sidewall insulating films 60 and 70 are composed of a deposited insulating film, or a thermally oxidized film of a silicon thin film when the gate electrode 4 is composed of a silicon thin film or the like.
Each of the above-mentioned single insulating films could not be set to a thickness less than a predetermined thickness because it would be electrically fragile and cause a short circuit between the gate electrode 4 and the silicide layer 12 or 13. On the other hand, if the gate sidewall insulating films 60 and 70 are set thick, the junction depth must also be set deep, but in ultra-fine transistors, an increase in the junction depth has the disadvantage of lowering the punch-through breakdown voltage.

[Object of the Invention] An object of the present invention is to provide a semiconductor device that can maintain the polarity of a polar diffusion layer and eliminate junction breakdown related to the wiring process. In particular, the main objective is to provide a semiconductor device having a structure that is not damaged by the process of forming contact holes, especially in ultrafine MO8 in which the source/drain diffusion layers are silicided.

An object of the present invention is to provide an ultrafine transistor in which a high melting point metal or a silicide film thereof is formed on a source/drain diffusion layer without causing a short circuit between a gate electrode and the metal or silicide layer.

Another object of the present invention is to provide a semiconductor device in which the source-drain junction depth is set to a desired depth independent of the gate sidewall insulating film thickness, and the breakdown voltage between the source and the train can be improved.

[Summary of the invention]

The present invention has discovered a new phenomenon in which an extremely shallow junction of 50 mm or less can be formed directly under a silicide layer at a low temperature of 600°C or less using the precipitation effect from the silicide layer, and the ultra-fine M
This paper concerns the resolution of problems found in the process of considering application to O8. 0 below the silicide layer. ] to 0.2 μm
In the conventional micro-111 IMO8 having an N+ or P+ diffusion layer having a depth of more than 100 nm, the above-mentioned problem does not lead to a fatal failure. The new precipitation phenomenon has been described by one of the inventors in previously filed Japanese Patent Application No. 58-226847, and will not be repeated here.

In the present invention, in order to prevent the damage 11 in which the doped silicide film and the horizontal beam junction immediately below it are removed when forming a contact hole in the interlayer insulating film prior to the All wiring process, after the silicide film is formed, A highly conductive film, such as a W film, which is resistant to the etching agent of the insulating film for one year is formed, and then an interlayer insulating film is deposited and contact holes are formed.

In the above structure, the underlying silicide film is not corroded in the process of opening holes in the interlayer insulating film, and the presence of the film such as W prevents the destruction of the horizontal beam junction due to the A111-3i product. Furthermore, since the formation of the above-mentioned highly conductive film can be carried out at a low temperature of 500° C. or lower, the influence of the edge of the bonding depth is ignored, and the horizontal beam bonding can be maintained.

Erosion of the underlying silicide film due to processing of the W film, etc., and an increase in the number of steps can be resolved by using a chemical vapor phase reaction method under which the W film, etc. is selectively deposited only on the underlying silicide film. There are no problems with fine opening caused by misalignment.

In view of the problems of the conventional transistor as shown in FIG. 8, the present invention consists of a gate sidewall insulating film made of a multilayer film of two or more layers. The occurrence of pinholes in an insulating film is extremely dependent on the substance of the substrate forming the insulating film and its surface condition. Since the above-mentioned surface condition is modified by the formation of the first insulating film, the influence of the substrate surface on the formation of the second and third layers and subsequent insulating films is different from that of the first insulating film formation. Therefore, even if pinholes occur in the second and subsequent insulating films, they occur at pinhole locations in the first insulating film. Therefore, by forming the gate sidewall insulating film into a multilayer structure, short circuits between the gate electrode and the source silicide layer or the drain silicide layer are significantly reduced.

By forming the gate sidewall insulating film in multiple layers, each insulating film layer can be assigned various roles. In other words, if the edge of the first layer gate sidewall insulating film is used as a mask for forming the source/drain diffusion layer, and then the source/drain silicide layer is formed after the second layer gate sidewall insulating film is formed, the gate A source/drain diffusion layer having a junction shallower than the sidewall insulating film thickness can be formed. Therefore, the optimal conditions for the junction depth can be set regardless of the gate sidewall insulating film thickness, and an ultra-fine transistor can be realized without reducing the punch-through breakdown voltage.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Please note that in the drawings, one local area is shown enlarged for convenience of explanation.

Embodiment 1 FIGS. 3 to 5 are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps.

A filled oxide film 2 having a thickness of 0.8 .mu.m is formed on a silicon substrate 1 having a P conductivity type and a resistivity of 10 .OMEGA. using a known device isolation technique, and then the surface of the silicon substrate 1 above the active region is exposed. From this state, a clean silicon oxide film having a thickness of 15 am was formed on the surface of the silicon substrate by thermal oxidation to form the gate insulating film 3. Subsequently, after depositing a silicon thin film with a thickness of 350 on by chemical vapor phase reaction, POCQ s
The resistance of the silicon thin film was reduced by a thermal diffusion method using a diffusion source. After removing the phosphosilicate glass containing a high concentration of phosphorus formed on the silicon thin film by the above thermal diffusion with a boiling water solution, the phosphosilicate glass to which a slight amount of phosphorus was added was removed.
It was deposited to a thickness of 2 μm. Next, the silicon thin film and the phosphosilicate glass film are processed using the same mask, and the gate electrode 4 is
, and a gate protection insulating film 5 were formed. The gate electrode length after processing was 0.8 μm. Next, a silicon oxide film with a thickness of 0.3 pm was deposited on the entire surface by a chemical vapor reaction using tetraethoxysilane (Si(Cx H30)4), and then a silicon oxide film was deposited in a direction perpendicular to the surface of the silicon substrate 1 by a known sputter etching method. Anisotropic etching is performed to proceed with etching, and the silicon oxide film in the flat portion is removed and left selectively only on the sidewalls of the gate electrode 4 and the gate protection insulating film 5, forming the gate sidewall insulating film 6. did. In this - state, the implanted ions are activated by ion implantation of P ions at an acceleration energy of 30 KeV and subsequent heat treatment at 950°C.
Then, an n-drain diffusion layer 8 was formed. In the above process, the ion implantation amount and heat treatment time are such that the junction depth of the n-diffusion layers 7 and 8 is 0.25 μm, and the surface impurity concentration is 3×10
It was set so that it read "am-". Next, the silicon oxide film remaining on the n-source diffusion layer 7 and the n-drain diffusion layer 8 was removed to expose the surface of the silicon substrate 1 again. Subsequently, a 100 nyn thick Ti film 22 was deposited on the entire surface by vacuum evaporation.

Next, at the energy condition of 6°KeV, l is blocked within the Ti film.
P ions of "X 101 Bdel-" were ion-implanted (Figure 3).

After the ion implantation of P ions, heat treatment was performed under conditions of 65° C. in a N2 atmosphere to form Ti5iz 9 and 10 in the region where the Ti film 22 and the silicon substrate 1 were in contact. Ti
The thickness of the 5iz film is 70! It was l111.

In the above-mentioned silicide formation heat treatment, some of the high concentration P ions implanted into the Ti film 22 are deposited at a high concentration directly under the Ti5iz films 9 and 10 and on the horizontal beams of 50 m or less during the formation of the Ti5iz film. Precipitated n-middle layers 11 and 12 are formed. After forming Ti5iz films 9 and 10, unreacted T
When the i film is removed with a mixed aqueous solution of hydrogen peroxide and ammonia water, the silicon oxide film and the Ti film on the phosphosilicate glass are not silicided and are easily removed, and the Ti film is selected only on the n- diffusion layers 7 and 8. TiSi2. Membranes 9 and 10 were left behind (FIG. 4).

After depositing the TiW film on the entire surface to a thickness of 0.2 μm using the sputtering method from the state shown in FIG. 4, a Ti5iz film 9
Diffusion-preventing films 131 and 141 were selectively formed by photolithography so as to cover the tops of the films 131 and 10. Next, an interlayer insulating film 15 made of a silicon oxide film slightly doped with phosphorus and having a thickness of 0.6 μm was deposited, and holes were formed in desired areas. Thereafter, an AQ film doped with Si was deposited over the entire surface, and desired electrodes and wiring including a source electrode 16 and a drain electrode 17 were formed by etching the AQ film according to a desired circuit configuration (FIG. 5).

In the semiconductor device manufactured through the above manufacturing process, the TL is
There were no defects in which the Siz films 9 and 10 were eroded, and no failure occurred in the n-middle layers 11 and 12 of the horizontal beams. That is, in the above manufacturing process, high contact resistance characteristics occurred frequently even within the same wafer in the junction electrical characteristics of semiconductor devices in which the diffusion prevention films 131 and 141 were not used for comparison, resulting in variations in characteristics. Considering the facts, this shows that an epoch-making improvement has been achieved. In this embodiment, holes were formed at desired locations in the interlayer insulating film 15 by a dry etching method using CF4 as a source.
Erosion is so slight that it can be almost ignored.

Example 2 FIG. 1 is a diagram showing a second embodiment of the present invention.

Using tungsten hexafluoride (WFe) in a hydrogen atmosphere from the state shown in FIG. 4 in the first embodiment, the reaction temperature was 350.
℃, pressure I Torr using a horizontal reactor 200++
W films 13 and 14 with a thickness of a were deposited.

Under the above deposition conditions, the W films 13 and 14 are the Ti5iz film 9.
and 10, and is not formed on the field oxide film 2 made of a silicon oxide film, the gate protection insulating film 5, etc. The above deposition was carried out at a deposition rate of 10 I/min. After the selective deposition of the 6W films 13 and 14, the interlayer insulating film 15 was formed and holes were formed at desired locations in accordance with the first embodiment, and Electrodes and wiring including a source electrode 16 and a drain electrode 17 were formed by processing an An vapor deposited film according to a desired circuit configuration.

In semiconductor devices manufactured through the above manufacturing process, T
W, which is a diffusion blocking film, is self-aligned with the i5iz films 9 and 10.
Since the films 13 and 14 are formed, there is no need to process and form a diffusion blocking film as in the case of Example 1. Therefore, a decrease in yield due to short circuits between the source and drain due to misalignment in the processing of the highly conductive diffusion blocking film can be avoided. This could be prevented, and the number of steps could be reduced compared to the first example. The W films 13 and 14 formed according to this example were not corroded at all by dry etching with CF4, and therefore were not affected by the openings in the interlayer insulating film 15. Furthermore, the W films 13 and 14 have a sufficient diffusion blocking effect on the diffusion of AQ constituting the source electrode 16 and the drain electrode 17. Even when subjected to heat treatment in a hydrogen atmosphere, no defects related to poor bonding such as bond penetration were observed, and good electrical characteristics were obtained.

Example 3 FIG. 6 is a diagram showing a third embodiment of the present invention.

In the second embodiment, after the formation of the gate sidewall insulating film 6, the fermented oxide film on the region where the source/drain diffusion layer is to be formed is removed, and a patent application previously filed by one of the inventors of the present invention is applied. Polycrystalline or amorphous silicon thin films 23 and 24 were selectively formed using the method described in Japanese Patent No. 58-76119. After that, the second or first. According to the example, ion implantation and activation heat treatment were performed to form an n-diffusion layer, and n-source diffusion! 47 and an n-drain diffusion layer 8 were formed. In addition, the above silicon 'uIII23 and 2
The formation of 4 is the 3n-source diffusion layer 7 in each of the above embodiments.
and n-ion implantation and subsequent activation heat treatment, which may be performed after forming the n-drain diffusion layer 8, and then perform the n-ion implantation step and activation heat treatment again into the silicon thin films 23 and 24. After that, according to the second embodiment, Ti5J x films 91 and 1.01. n+ precipitated layer 1
11 and 121. Diffusion prevention film 132 by selective deposition of W
, and 142 were sequentially performed to manufacture a semiconductor device.

In the semiconductor device manufactured through the above manufacturing process, similarly to the semiconductor device based on the second embodiment, the diffusion prevention films 132 and 142 made of W completely eliminate the influence of the processing of the interlayer gaps 911!15. There was no problem at all with regard to the effect on the removal of Afl and the penetration of Afl. In particular, the semiconductor device based on this embodiment has the characteristics described in Japanese Patent Application No. 58-76119, that is, it has superior voltage resistance characteristics compared to the semiconductor device based on the second embodiment, and is free from defects such as poor bonding. It was possible to obtain the product with a good yield without any formation.

Embodiment 4 FIGS. 9 to 11 and FIG. 7 are cross-sectional views showing a fourth embodiment of the present invention in the order of manufacturing steps.

A filled oxide film 2 having a thickness of 0.8 .mu.m is formed on a silicon substrate 1 having a P conductivity type and a resistivity of 10 .OMEGA.-■ using a known device isolation technique, and then the surface of the silicon substrate 1 above the active region is exposed. From this state, a clean silicon oxide film with a thickness of 15 mm was formed on the surface of the silicon substrate by thermal oxidation to form the gate insulating film 3. Subsequently, a silicon thin film with a thickness of 350 m was deposited by chemical vapor phase reaction, and then the resistance of the silicon thin film was reduced by a thermal diffusion method using POCQ s as a diffusion source.

The silicophosphate glass formed on the silicon thin film by the above diffusion was removed with a dilute aqueous hydrofluoric acid solution, and silicophosphate glass to which a slight amount of phosphorus had been added was deposited again to a thickness of 0.2 μm.

Next, the silicon thin film and the silicophosphate glass film were processed using the same mask to form a gate electrode 4 and a gate protection insulating film 5. Next, tetraethoxysilane (Si CCxHδ○
) A silicon oxide film with a thickness of 0.15 μm was deposited on the entire surface by chemical vapor phase reaction according to step 4), and anisotropic etching was performed using a well-known sputter etching method in which etching progressed only in the direction perpendicular to the surface of the silicon substrate 1. Then, the flat silicon oxide film was removed and left selectively only on the sidewalls of the gate electrode 4 and gate protection insulating film 5, forming first gate sidewall insulating films 6 and 7. From this state, the implanted ions are activated by ion implantation of phosphorus (P) ions at an acceleration energy of 30 KeV and subsequent heat treatment at a temperature of 950'C. was formed. In the above process, the ion implantation amount and heat treatment time are such that the junction depth of n- diffusion layers 8 and 9 is 0.15 μm, and the surface impurity concentration is 3XIQ"ae-"
(Fig. 9).

From this state, chemical reciprocity using 5i(CzH50)4 was applied again, and a second silicon oxide film having a thickness of 0.15 μm was deposited. Thereafter, sputter etching was performed again to selectively leave the second silicon oxide film only on the side surfaces of the first gate sidewall insulating films 6 and 7 to form second gate sidewall insulating films 10 and 11. In this state, the silicon oxide film 3 remaining on the n-source diffusion layer 8 and the n-drain diffusion layer 9 was removed to selectively expose the surface of the silicon substrate 1. Next, 100mm thick titanium (
φi) Energy condition 1 that is blocked within the Ti film 123 after the film 123 is entirely deposited by sputtering method
, 60 KeV and 1×10 18 ions were implanted (FIG. 10).

After the P ion implantation, heat treatment is performed in a N2 atmosphere at 650° C. to form titanium silicide (hereinafter referred to as Ti5iz) in the region where the Ti film 123 and the silicon substrate 1 are in contact.
(the ratio of Si and Si does not need to be 1:2) layers 12 and 13
was formed. The thickness of the Ti5iz layer was 70 mm.

In the above heat treatment for forming the silicide layer, some of the high concentration P ions implanted into the Ti film 123 become Tj, Si
When forming the z layer, Ti5iz Ml 2 and 13 are precipitated at a high concentration and with a polarity of 50 mm or less, forming an n middle layer. The above-mentioned n middle layer enables good ohmic contact between the n-source diffusion layer 8 and the n-drain diffusion layer 9 and the Ti5iz layers 12 and 13. After forming the Ti5iz layers 12 and 13, if the unreacted Ti film is removed with a mixed aqueous solution of hydrogen peroxide and ammonia water, the Ti film on the silicon oxide film or silicate glass is not silicided and is easily removed. , T only on the n-diffusion layers 12 and 13
The i5iz layers 12 and 13 remained (Figure 11).

From the state shown in FIG. 11, a silicon oxide film slightly doped with phosphorus was deposited to a thickness of 0.6 μm to form an interlayer insulating film 14, and holes were formed at desired locations.

A Ti film of approximately 0.2 μm was deposited while leaving the photoresist film used in the hole-opening step described above. When the photoresist film was removed in this state, the Ti film other than the openings was also removed at the same time, and the TiW films 15 and 16 were selectively left only in the openings.

Thereafter, an AQ film was deposited on the entire surface, and the AQ film was etched according to a desired circuit configuration to form electrodes and wiring including a source electrode 17 and a drain electrode 18 (FIG. 7).

The transistor manufactured by completing the above manufacturing process has the same film thickness of 0.3 μm, and has a gate sidewall insulating film composed of a single layer, as shown in FIG. Compared to the conventional method, short-circuit defects between the gate electrode and the source or the drain silicide layer have been dramatically improved. In other words, the short-circuit defects in the latter were mainly concentrated in the wafer periphery, and were found in 21 out of 148 measurement elements, whereas in the transistors based on this example, short-circuit defects were observed in the same number of measurement devices. Only 3 defects were found.

Furthermore, in the transistor based on this embodiment in which the source/drain diffusion layer is silicided, the junction depth between the n-source diffusion layer and the n-drain diffusion layer 9 can be set independently of the gate sidewall insulation thickness. , 0.15 μm. In the conventional transistor shown in FIG. 2 and having the same gate sidewall insulating film thickness of 0.3 μm as in this embodiment, the above junction depth is 0.3 μm.
The depth was twice that of this example. Source of both
When the drain-to-drain breakdown voltage was measured, the former was about 1.5 V higher than the latter, and a high breakdown voltage value of 9.5 V was obtained. As a result of computer analysis using two-dimensional numerical analysis of the limiting factors for the withstand voltage of both, it was found that the latter, that is, the lateral pressure of conventional structural elements, is due to the punch-through phenomenon between the source and drain, and the former is due to avalanche precipitation. Estimated. From the above analysis.

Based on this embodiment, the source/drain junction depth could be made shallower independently of the gate sidewall insulating film, and the punch-through low voltage could be increased.

In this embodiment, for convenience of explanation, an example in which the first gate sidewall insulating films 6 and 7 and the gate protective insulating film 5 are formed in separate processes has been described, but after processing the gate electrode 4, low temperature wet oxidation A thick oxide film is selectively formed on the top and sidewall portions of the gate electrode 4 into which impurities have been implanted at a high concentration using a method, etc., and at the same time, a thick oxide film is formed on the gate protection insulating film 5 and the first gate sidewall insulating films 6 and 7. may be formed. That is, there is no problem even if the first gate sidewall insulating films 6 and 7 are thermally oxidized films and the second gate sidewall insulating films 10 and 11 are deposited films.

〔Effect of the invention〕

According to the present invention, an ultra-fine semiconductor device is completely unaffected by variations in the processing conditions of an interlayer insulating film, and AQ punching and defects can be completely prevented. Furthermore, according to the present invention, the diffusion prevention film can be formed at a low temperature of 400° C. or lower and in a self-aligned manner with the source/drain regions, thereby maintaining the polar source/drain junction and preventing defects such as short circuits between the source and drain. This has the effect of making it possible to realize ultra-fine semiconductor devices with high breakdown voltage and high gain without any problems.

In the above explanation, the semiconductor substrate has been described, but the above is for the purpose of simplifying the explanation, and the above also refers to an eviquitial layer on the semiconductor substrate and a so-called well diffusion layer formed deep within the semiconductor substrate. The present invention can be applied in the same way as the semiconductor substrate.

In each embodiment of the present invention, an example in which titanium silicide is used as the silicide layer has been described, but the silicide layer may be made of other metal silicides, such as W, Pt, Pd, Ta.
, Cr, Go, Nb, Hf.

There is no problem in changing the temperature using a high melting point metal such as Ni or Zr or a transition metal silicide. Furthermore, n-sauce
There is nothing wrong with replacing the diffusion layer and the n-drain diffusion layer with a highly concentrated n+ source diffusion layer and n+ drain diffusion layer, and the so-called Lightly Dopad
It is obvious that the present invention can also be applied to a drain diffusion layer structure called a + Drain (L D D ) structure and a double drain structure. Furthermore, in each embodiment, a so-called n-channel type structure in which the source/drain diffusion layers are of n conductivity type was explained, but the above is a so-called P-channel type structure having p-, p÷ type source/drain diffusion layers. It is clear that the present invention is also effective for. Therefore, it goes without saying that the present invention is also applicable to complementary MO8 field effect transistors and semiconductor integrated circuit devices in which a large number of transistors are configured on the same substrate.

Incidentally, in each of the above embodiments, TiW is used as an example of the diffusion prevention film.
, W film is shown, but in addition, TiN, Ti, Ta
, or a good conductive thin film that prevents the diffusion of AQ and is not affected during processing of the interlayer insulating film, such as a Ta film.

Further, according to the present invention, the pinhole density between the gate electrode and the silicide layer on the source/drain diffusion layer can be dramatically reduced, so that short-circuit defects between terminals of the transistor can be significantly eliminated. Further, according to the present invention, since the source/drain diffusion layer is introduced from the end of the first gate sidewall insulating film, a source/drain junction having a shallow junction can be formed regardless of the cumulative thickness of the gate sidewall insulating film, and punching is possible. This has the effect of improving the source-drain breakdown voltage due to the through phenomenon.

Note that in the claims, expressions such as a first insulating film, a second insulating film, and even a third insulating film are used, but these are not necessarily limited to single-layer insulating films. Even if any of the insulating films is made of multilayer insulation, it does not depart from the spirit of the present invention.

Furthermore, the present invention was previously filed in Japanese Patent Application No. 58-76 by the present inventors.
It is clear that this invention can also be applied to a semiconductor device as previously filed as No. 119, that is, a structure in which source/drain regions are stacked on a semiconductor substrate, or a structure in which a gate electrode is buried below the surface of a semiconductor substrate. It is.

Furthermore, in the embodiments of the present invention, for convenience of explanation, a so-called n-channel transistor having an n-type source/drain diffusion layer in a P-type substrate has been described. A so-called P-channel MO8 type field effect transistor having a P-type source/drain region, and a complementary MOsg configured in a single substrate of a p-channel and n-channel MO9O9 type field effect transistor.
It is clear that the present invention can also be applied to field effect transistors and semiconductor integrated circuit devices in which a large number of transistors are configured within the same semiconductor substrate.

In the fifth embodiment of the present invention, for convenience of explanation, titanium silicide is used as the silicide layers 12 and 13, but the above is not limited to titanium silicide, and may include W, Mo, Ta, and Pd.

There is no problem in replacing it with high melting point metals such as Pt, Cr, Go, Ni, Zr, Nb, Hf, silicides of transition metals, or even with the above metals themselves.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a second embodiment of the present invention, which is a typical example of the present invention. FIG. 2 is a cross-sectional view of a conventional semiconductor device, FIGS. 3 to 5 are cross-sectional views showing the first embodiment of the present invention in order of process, and FIG. 6 is a cross-sectional view of the third embodiment of the present invention. 7 is a sectional view showing an embodiment of the present invention, FIG. 8 is a sectional view showing a conventionally known semiconductor device, and FIGS.
The figures are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. ],...Substrate, 2...Insulating film, 3...Gate insulating film, 4...11 factor V3 figure 4 figure, D

Claims (1)

[Claims] 1. A diffusion layer having a conductivity type opposite to that of a semiconductor substrate, a metal silicide layer configured to cover at least a portion of the diffusion layer, and a metal silicide layer configured to cover at least a portion of the diffusion layer. In a semiconductor device having an insulating film, the insulating film is formed on the metal silicide layer via a conductive film having an etching rate slower than the etching rate of the metal silicide film with respect to the etching material of the insulating film. A semiconductor device characterized by: 2. A semiconductor device according to claim 1, wherein the conductive film is configured in a self-aligned relationship with the metal silicide layer. 3. Parts of the first and second diffusion layers having a conductivity type opposite to that of the semiconductor substrate are covered by a gate electrode via a first insulating film, and a second insulating film is formed on a side wall of the gate electrode. In the semiconductor device, the diffusion layer is introduced at the end of the second insulating film, and a third insulating film provided adjacent to the second insulating film is formed on the diffusion layer, and a third insulating film provided adjacent to the second insulating film; A semiconductor device characterized in that a metal silicide layer is provided adjacent to the third insulating film.