JPS6214493U - - Google Patents

Info

Publication number
JPS6214493U
JPS6214493U JP10644985U JP10644985U JPS6214493U JP S6214493 U JPS6214493 U JP S6214493U JP 10644985 U JP10644985 U JP 10644985U JP 10644985 U JP10644985 U JP 10644985U JP S6214493 U JPS6214493 U JP S6214493U
Authority
JP
Japan
Prior art keywords
data
display
digital display
digital
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10644985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10644985U priority Critical patent/JPS6214493U/ja
Publication of JPS6214493U publication Critical patent/JPS6214493U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例を示す表示データ
の表示システム構成図、第2図は本考案に使用す
るデイジタル表示器の一実施例を示す構成図、第
3図および第4図は従来のデイジタル表示器を示
したもので、第3図はスタテイツク接続図、第4
図はパーテイライン接続図である。 1はS/P変換部、2はデータ検出回路、3は
メモリ回路、4はアドレス検出回路、5はアドレ
ス設定部、6はアドレス比較回路、7は符号検定
回路、8はアンド回路、9はセグメントドライバ
、10はデイジタル表示部、51はP/S変換部
、52は伝送ラインインターフエイス、DPV
〜DPVはデータ表示装置、DP,DP,D
はデイジタル表示器、DOVはデータ出力装
置。
FIG. 1 is a block diagram of a display system for display data showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of a digital display used in the present invention, and FIGS. 3 and 4 are This shows a conventional digital display, with Figure 3 being a static connection diagram and Figure 4 being a static connection diagram.
The figure is a party line connection diagram. 1 is an S/P conversion section, 2 is a data detection circuit, 3 is a memory circuit, 4 is an address detection circuit, 5 is an address setting section, 6 is an address comparison circuit, 7 is a sign verification circuit, 8 is an AND circuit, and 9 is a Segment driver, 10 is a digital display section, 51 is a P/S conversion section, 52 is a transmission line interface, DPV 1
~DPV 2 is a data display device, DP, DP 1 , D
P3 is a digital display, DOV is a data output device.

Claims (1)

【実用新案登録請求の範囲】 (1) データ出力装置より伝送される表示データ
を監視制御装置などに数字・記号・文字などとし
てセグメント表示数デイジタル表示器において、 前記データ出力装置より送信される直列符号伝
送データを受信し並列符号化する手段と、この並
列符号化されたデータを検出した後記憶するメモ
リ手段と、前記並列符号化信号のアドレスを検出
し、検出されたアドレスと前もつて設定されたア
ドレスを比較し前記メモリ手段に記憶された当該
データを出力させるアドレス比較部と、メモリ手
段よりの出力をセグメントドライバを介して導入
デイジタル表示するデイジタル表示部とで前記デ
イジタル表示器を構成したことを特徴としたデイ
ジタル表示器。 (2) 前記デイジタル表示器を複数個設けてデー
タ表示装置を構成し各デイジタル表示器の入力は
、互に共通して接続したことを特徴とした実用新
案登録請求の範囲第1項記載のデイジタル表示器
[Claims for Utility Model Registration] (1) Display data transmitted from a data output device is displayed as numbers, symbols, characters, etc. on a monitoring and control device, etc. In a digital display with a number of segments, serial data transmitted from the data output device means for receiving and parallel-encoding code transmission data; memory means for detecting and storing the parallel-encoded data; detecting an address of the parallel-encoded signal and presetting the detected address and the detected address; The digital display device comprises an address comparison section that compares the addresses and outputs the data stored in the memory means, and a digital display section that digitally displays the output from the memory means through a segment driver. A digital display featuring these features. (2) A digital device according to claim 1 of the utility model registration, characterized in that a plurality of said digital displays are provided to constitute a data display device, and the inputs of each digital display are commonly connected to each other. display.
JP10644985U 1985-07-12 1985-07-12 Pending JPS6214493U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10644985U JPS6214493U (en) 1985-07-12 1985-07-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10644985U JPS6214493U (en) 1985-07-12 1985-07-12

Publications (1)

Publication Number Publication Date
JPS6214493U true JPS6214493U (en) 1987-01-28

Family

ID=30981817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10644985U Pending JPS6214493U (en) 1985-07-12 1985-07-12

Country Status (1)

Country Link
JP (1) JPS6214493U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55155391A (en) * 1979-05-22 1980-12-03 Tokyo Shibaura Electric Co Digital display unit
JPS5880694A (en) * 1981-11-09 1983-05-14 日本電気株式会社 Display
JPS59100496A (en) * 1982-11-30 1984-06-09 松下電工株式会社 Display

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55155391A (en) * 1979-05-22 1980-12-03 Tokyo Shibaura Electric Co Digital display unit
JPS5880694A (en) * 1981-11-09 1983-05-14 日本電気株式会社 Display
JPS59100496A (en) * 1982-11-30 1984-06-09 松下電工株式会社 Display

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