JPS62146018A - Method for testing frequency dividing circuit - Google Patents
Method for testing frequency dividing circuitInfo
- Publication number
- JPS62146018A JPS62146018A JP60288835A JP28883585A JPS62146018A JP S62146018 A JPS62146018 A JP S62146018A JP 60288835 A JP60288835 A JP 60288835A JP 28883585 A JP28883585 A JP 28883585A JP S62146018 A JPS62146018 A JP S62146018A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency dividing
- output signal
- signal
- dividing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title description 2
- 230000007704 transition Effects 0.000 claims abstract description 4
- 230000002950 deficient Effects 0.000 abstract description 4
- 230000003111 delayed effect Effects 0.000 abstract description 3
- 238000010998 test method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は分周回路試験方法に係り、特にｌ、８１化した
分周回路の試験力泳に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a frequency dividing circuit testing method, and more particularly to testing of a frequency dividing circuit of 1,81 scale.
分周回路を１，８１化して試験する場合、分周比が増す
に従って、試験時間や試験用１０グラム等が増加する。When testing a frequency divider circuit with a frequency dividing circuit of 1.81, the test time and test 10 grams increase as the frequency division ratio increases.
例えば％１０ビットの分周回路であれば、杓子パターン
のプログラムが必要であり、２０ビツトあれば約百万パ
ターンが必要となる。For example, a %10-bit frequency divider circuit requires a program in a ladder pattern, and a 20-bit frequency divider requires approximately one million patterns.
このため従来のこの種の試験回路は、第２図の様な回路
構成をしていた。同図において、被分周の入力信号１１
が入力されるｎ分周の分周回路１と、入力信号１１と分
周回路１の出力信号１３とか入力される切換回路２０と
、切換回路２０の出力信号１６か入力されるｎ分周の分
周回路２とが示されている。ここで、切換回路２０は、
二つのＡＮＬ）回路３，４と、０几回路５と、インバー
タ６とから構成され、制御信号１０に工り、入力信号１
１と分周回路１の出力信号１３とのうちどちらかを選択
して出刃信号１６とする機能を弔する。For this reason, conventional test circuits of this type have a circuit configuration as shown in FIG. In the figure, the input signal 11 to be divided
, a switching circuit 20 to which the input signal 11 and the output signal 13 of the frequency dividing circuit 1 are input, and a switching circuit 20 to which the output signal 16 of the switching circuit 20 is input. A frequency dividing circuit 2 is shown. Here, the switching circuit 20 is
It is composed of two ANL) circuits 3 and 4, an zero circuit 5, and an inverter 6, and a control signal 10 and an input signal 1
1 and the output signal 13 of the frequency divider circuit 1, the function is to select either one of the output signal 13 and use it as the cutting signal 16.
出力として、出力信号１３と％ｎ分周の分周回路２の出
力信号１７とかある。As outputs, there are an output signal 13 and an output signal 17 of the frequency dividing circuit 2 divided by %n.
この分周回路１．２を試験する時には、テスト信号１０
をｌ（”に固定し、クロ・ツク信号１１を分周回路１の
出力信号１３と同時に、切換回路２０を通って、信号１
６として分周回路２に入力し、ｍ ｘ ｎ分周の分周回
路を、ｍ又はｎのどちらか大きい万の分周回路の試験条
件と同じ条件により試験できる。When testing this frequency divider circuit 1.2, the test signal 10
is fixed to l('', and the clock signal 11 is passed through the switching circuit 20 simultaneously with the output signal 13 of the frequency divider circuit 1, and the signal 1 is
6 is input to the frequency divider circuit 2, and the m x n frequency divider circuit can be tested under the same conditions as the test conditions for the 10,000 frequency divider circuit, whichever is larger, m or n.
しかし、テスト信号を′Ｈ”に固定して試験するため、
論理ＡＮＤ回路４及びインバータ６の動作が確認できす
、不良品混入の可能性が残るとともに、出方信号１３用
の端子を余分に必要とする等の欠点かあった。However, since the test signal is fixed at 'H' for testing,
The operation of the logical AND circuit 4 and the inverter 6 could not be confirmed, there remained a possibility that defective products were mixed in, and there were drawbacks such as the need for an extra terminal for the output signal 13.
本発明の目的は、前記欠点が解決され、試験のためだけ
に使用する出力端子を省き、不良品混入の可能性を低減
するようにした分周回路試験方法を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency divider circuit testing method in which the above-mentioned drawbacks are solved, an output terminal used only for testing is omitted, and the possibility of defective products being mixed in is reduced.
本発明の構成は、被分周の入力信号か印加される第１の
分周回路と、制御信号により、前記入力信号と前記第１
の分周回路の出力信号とのうちとちらかを選択して出力
する切換回路の出力信ｇを入力とする第２の分周回路と
を試験する分周回路試験方法において、前記第１．第２
の分周回路の試験中、前記制御信号を少なくとも２回遷
移させ、前記切換回路を切り換えることを特徴とする。The configuration of the present invention includes a first frequency divider circuit to which an input signal to be divided is applied, and a control signal that divides the input signal and the first frequency divider circuit.
and a second frequency divider circuit which inputs the output signal g of a switching circuit which selects and outputs one of the output signals of the frequency divider circuit of the above-mentioned first frequency divider circuit. Second
The control signal is transitioned at least twice to switch the switching circuit during the test of the frequency dividing circuit.
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図（ａｌは本発明の一実施例の分周回路試験方法を
示すプロヅク因、第１図（ｂｌは第１図（ａｔの回路の
各部のタイムチャートでおる。FIG. 1 (al is a production factor showing a frequency dividing circuit test method according to an embodiment of the present invention, and FIG. 1 (bl is a time chart of each part of the circuit in FIG. 1 (at).
これらにおいて、被分周の入力信４１１が入力されるｍ
分周の分周回路ｌと、前記入力信号１１または分周回路
ｌの出力信号１３が出力信号１６として出力される切換
回路２０と、この切換回路２０の出力信号１６を入力と
するｎ分周の分周回路２とか示されている。切換回路２
０は、二つのＡＮｉＪ回路３，４と、インバータ６と、
ＯＲ回路５とからなり、制御信号ｌＯにより、前記２信
号の切換えが行われる。ここで、全体の出力としては、
分周回路２の出力信号１７のみでめる。また、ｍ。In these, the frequency-divided input signal 411 is inputted m
A frequency dividing circuit l, a switching circuit 20 from which the input signal 11 or the output signal 13 of the frequency dividing circuit l is outputted as the output signal 16, and a frequency dividing circuit 20 which receives the output signal 16 of the switching circuit 20 as an input. A frequency divider circuit 2 is shown. Switching circuit 2
0 includes two ANiJ circuits 3 and 4, an inverter 6,
It consists of an OR circuit 5, and switching between the two signals is performed by a control signal lO. Here, the overall output is:
Only the output signal 17 of the frequency dividing circuit 2 is available. Also, m.
ｎは自然数で、ｍ≦ｎの関係にあるＱ
まず、テスト用制御信号１０を１Ｈ”に保ち、クロヴク
入力信号１１を分周回路ｌとＡＮＬ）口開３とに入力す
る。制御信号１０が′Ｈ”であるので、入力信号１１は
切換回路２０を通り、出刃信号１６となって、分周回路
２に入力する。n is a natural number, and Q satisfies the relationship m≦n. First, the test control signal 10 is kept at 1H", and the Krovk input signal 11 is input to the frequency divider circuit 1 and the ANL opening 3. The control signal 10 is Since it is 'H', the input signal 11 passes through the switching circuit 20, becomes the blade signal 16, and is input to the frequency dividing circuit 2.
このため、第１図１ｂ＋に示す区間Ａにおいては、分局
回路ｌ及び２は同一のクロックにより、同一タイミング
で分周動作を行う。Therefore, in the section A shown in FIG. 1, 1b+, the division circuits 1 and 2 perform frequency division operations using the same clock and at the same timing.
次に、分局が（ｍ−２］まで進んだ所で入力信号１１を
′Ｌ＃と設定すると、分周回路ｌの出力信号１３が切換
回路２０を通り、出力信号１６となって、分周回路２に
入力する。このため、第１図１ｂ＋に示す区間Ｂにおい
ては、出力信号１６は１クロック分ぬけた波形となり、
分周回路２では、このためｌクロック分遅れることにな
る。Next, when the input signal 11 is set to 'L#' when the division has advanced to (m-2), the output signal 13 of the frequency divider circuit l passes through the switching circuit 20, becomes the output signal 16, and It is input to the circuit 2. Therefore, in the section B shown in FIG. 1b+, the output signal 16 has a waveform with one clock difference,
Therefore, the frequency dividing circuit 2 is delayed by l clocks.
次に、分周かｍを数えた時に、入力信号１１を“Ｈ”に
もどすと、クロックの入力信号１１が出刃信号１６とな
り、分周回路２に入力する。Next, when the frequency division m is counted, the input signal 11 is returned to "H", and the clock input signal 11 becomes the cutting signal 16 and is input to the frequency dividing circuit 2.
そこで、制鈎他号ｌＯを常に”Ｈ″′に保っていれは立
ち下がり１７ａのタイミングで波形の遷移か行なわれる
はすであるか、以上説明した方法によると、立ち下が９
１７ａ′のタイミング、即ちｌクロック分だけ遅れた波
形で、波形の遷移が行われる。Therefore, if the control hook lO is always kept at "H"', the waveform transition will occur at the timing of the falling edge 17a.According to the method explained above, the falling edge is 9.
The waveform transition is performed at the timing 17a', that is, the waveform is delayed by l clocks.
ここで、分周回路１の動作が不良であれば、出力信号１
３の波形はタイムチャートどおり出す、出力信号１７の
タイミングもずれることになる。Here, if the operation of the frequency divider circuit 1 is defective, the output signal 1
The waveform No. 3 is output according to the time chart, but the timing of the output signal 17 is also shifted.
これにより、出力信号１６を観測することなく、分周回
路ｌの観測が行える。Thereby, the frequency divider circuit l can be observed without observing the output signal 16.
また、制＠ｌ信号１０を切換て試験するため、切換回路
２０の各回路の確認も行える。Furthermore, since the control @l signal 10 is switched and tested, each circuit in the switching circuit 20 can be checked.
尚本実施例では、分周回路を２つ、切換回路を１つの場
合について説明しているか、分周回路及び切換回路か増
加しても同様の効果を侍られるのは明かでおる。In this embodiment, a case is explained in which there are two frequency dividing circuits and one switching circuit, but it is clear that the same effect can be obtained even if the number of frequency dividing circuits and switching circuits is increased.
以上説明した工うに、本発明によれは、前段の分周回路
の出力か遷移する前後の数クロック分たけ、テスト１８
号を反転することによ＃）％余分な出力信号用テスト端
子なしに、また切換ＩＰ！Ｊ路の動作を含めて分周回路
の試験をできるという効果か得られる。As described above, according to the present invention, the test 18 is performed several clocks before and after the output of the frequency dividing circuit in the previous stage changes.
By inverting the signal #)% without extra output signal test terminal, also switching IP! This provides the advantage of being able to test the frequency divider circuit including the operation of the J path.
第１図（ａｌは本発明の一実施例の分周回路試験方法を
示すブロック図、第１図＋ｂ＋は第１図（ａｌの回路の
動作を示すタイムチャート、第２図は従来の分周回路試
験方法を示すブロック図である。
１．２−・・・・・分周回路、３．４・・・・・・ＡＮ
Ｄ回路。
５・・・・・・ＯＲ回路、６・・・・・・インバータ、
ｌＯ・・・・・・テスト用制御信号、１１・・・・・・
クロック入力信号、１３゜１７・・・・・・分周回路出
力信号、２０・・・・・・切換回路。
第１図（勾
千１図（ｂ）Figure 1 (al is a block diagram showing the frequency dividing circuit test method of one embodiment of the present invention, Figure 1 + b + is a time chart showing the operation of the circuit in Figure 1 (al), Figure 2 is a conventional frequency dividing circuit test method. It is a block diagram showing a circuit test method. 1.2-... Frequency divider circuit, 3.4...... AN
D circuit. 5...OR circuit, 6...Inverter,
lO...Test control signal, 11...
Clock input signal, 13°17... Frequency divider circuit output signal, 20... Switching circuit. Figure 1 (Kosen 1 (b)
Claims (1)
信号により、前記入力信号と前記第１の分周回路の出力
信号とのうちどちらかを選択して出力する切換回路の出
力信号を入力とする第２の分周回路とを試験する分周回
路試験方法において、前記第１、第２の分周回路の試験
中、前記制御信号を少なくとも２回遷移させ、前記切換
回路を切り換えることを特徴とする分周回路試験方法。a first frequency dividing circuit to which a frequency-divided input signal is applied; and a switching circuit that selects and outputs either the input signal or the output signal of the first frequency dividing circuit according to a control signal. In the frequency divider circuit testing method of testing a second frequency divider circuit that receives an output signal as input, during testing of the first and second frequency divider circuits, the control signal is made to transition at least twice, and the switching circuit A frequency divider circuit testing method characterized by switching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288835A JPS62146018A (en) | 1985-12-20 | 1985-12-20 | Method for testing frequency dividing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288835A JPS62146018A (en) | 1985-12-20 | 1985-12-20 | Method for testing frequency dividing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62146018A true JPS62146018A (en) | 1987-06-30 |
Family
ID=17735363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60288835A Pending JPS62146018A (en) | 1985-12-20 | 1985-12-20 | Method for testing frequency dividing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62146018A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01202025A (en) * | 1988-02-08 | 1989-08-15 | Mitsubishi Electric Corp | Mode switching circuit |
| US5731728A (en) * | 1995-11-13 | 1998-03-24 | National Semiconductor Corporation | Digital modulated clock circuit for reducing EMI spectral density |
| US7515646B2 (en) | 2004-02-05 | 2009-04-07 | Lexmark International, Inc. | Method and apparatus for reducing EMI emissions for data signals traveling over a data pathway |
-
1985
- 1985-12-20 JP JP60288835A patent/JPS62146018A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01202025A (en) * | 1988-02-08 | 1989-08-15 | Mitsubishi Electric Corp | Mode switching circuit |
| US5731728A (en) * | 1995-11-13 | 1998-03-24 | National Semiconductor Corporation | Digital modulated clock circuit for reducing EMI spectral density |
| US7515646B2 (en) | 2004-02-05 | 2009-04-07 | Lexmark International, Inc. | Method and apparatus for reducing EMI emissions for data signals traveling over a data pathway |
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