JPS6214860U - - Google Patents
Info
- Publication number
- JPS6214860U JPS6214860U JP10576485U JP10576485U JPS6214860U JP S6214860 U JPS6214860 U JP S6214860U JP 10576485 U JP10576485 U JP 10576485U JP 10576485 U JP10576485 U JP 10576485U JP S6214860 U JPS6214860 U JP S6214860U
- Authority
- JP
- Japan
- Prior art keywords
- output
- converter
- horizontal synchronization
- oscillation circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dc-Dc Converters (AREA)
Description
第１図は本考案の一実施例を示す回路ブロツク
図、第２図は同要部波形説明図を、それぞれ示す
。
１……電圧制御型発振回路、９……位相比較回
路、４……コンパレータ、３……基準電圧発生回
路、８……分周回路。
FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram illustrating waveforms of the main parts thereof. DESCRIPTION OF SYMBOLS 1... Voltage controlled oscillation circuit, 9... Phase comparison circuit, 4... Comparator, 3... Reference voltage generation circuit, 8... Frequency dividing circuit.
Claims (1)
バツク出力を重畳して成る比較信号と、基準電圧
とを入力するコンパレータの出力によりスイツチ
ングトランジスタの導通期間を制御して出力段の
電圧レベルを制御するＤＣ―ＤＣコンバータに於
て、 前記発振回路を、水平同期パルスを基準入力と
しその発振周波数を水平同期周期の整数倍に設定
するＰＬＬ回路で構成することを特徴とするビデ
オカメラ用ＤＣ―ＤＣコンバータ。[Claims for Utility Model Registration] The conduction period of the switching transistor is controlled by the output of a comparator which inputs a reference voltage and a comparison signal formed by superimposing the DC feedback output from the output stage side on the output of the oscillation circuit. In the DC-DC converter that controls the voltage level of the output stage, the oscillation circuit is configured with a PLL circuit that uses a horizontal synchronization pulse as a reference input and sets its oscillation frequency to an integral multiple of the horizontal synchronization period. DC-DC converter for video cameras.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10576485U JPS6214860U (en) | 1985-07-11 | 1985-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10576485U JPS6214860U (en) | 1985-07-11 | 1985-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6214860U true JPS6214860U (en) | 1987-01-29 |
Family
ID=30980496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10576485U Pending JPS6214860U (en) | 1985-07-11 | 1985-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6214860U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0284629U (en) * | 1988-12-14 | 1990-07-02 |
-
1985
- 1985-07-11 JP JP10576485U patent/JPS6214860U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0284629U (en) * | 1988-12-14 | 1990-07-02 |
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